Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

Acquiring data from files

Altera_Forum
Honored Contributor II
1,340 Views

I am trying to multiply a series of values that I am getting from txt files. 

My ideia is to get the data from 1 file, multiply for every data from the second file, get the second valor from the first file and again multiply it with all the values in the second file and so on. 

Can anyone give me a light? 

 

 

 

 

estimulo: process 

variable linha : LINE; 

variable valor1, valor2 : std_logic_vector(tamanho-1 downto 0); 

variable decisao : boolean; 

begin 

file_open(constante, "C:/Users/Eduardo/Desktop/Pos/VHDL/projfinal/proj7/vhdl/constante.txt", read_mode); 

file_open(variavelx, "C:/Users/Eduardo/Desktop/Pos/VHDL/projfinal/proj7/vhdl/variavelx.txt", read_mode); 

wait until (rst = '0'); 

report "fim do reset"; 

while not endfile(variavelx) loop 

readline(variavelx, linha); 

read (linha, valor2); 

b_i <= (unsigned(valor2(tamanho-1 downto 0))); 

 

while not endfile(constante) loop 

readline(constante, linha); 

read (linha, valor1); 

a_i <= (unsigned(valor1(tamanho-1 downto 0)));  

read (linha, decisao); 

caso <= decisao;  

report "subindo valores"; 

wait for 3*clk_period; 

end loop;
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
455 Views

What specific problems are you having? 

This code does no multiplying.
0 Kudos
Reply