Hello,Is it possible to add nets for signaltap debugging using VHDL attributes ?
Hi,Do you want attributes to be monitored using signaltap? Hope below links helps you. https://alteraforum.com/forum/showthread.php?t=53741 Refer session 7.1ftp://ftp.altera.com/up/pub/tutorials/de2/digital_logic/tut_signaltapii_vhdlde2.pdf Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
If you are referring to mark_debug attributes that xilinx uses, then no. Altera let's you search for nets from different lists, either HDL, synth or p&r net names. Altera also tends to preserve names logically rather than the terrible names xilinx come up with.