Address comparator

[Altera_Forum]

Hello, 

 1)I have written a verilog module which compares 4 addresses to check if any of them are equal.  - I have used xnor to compare the address. So a value of 1 indicates that the addresses are equal. (The simulation is correct till this point)  2)Next according to which addresses are equal I want to output a particular value. (I am not getting the output for this). I have used if-else statements to compare if the values are equal to 1 and accordingly I am setting a particular value to the output. (So if all the 4 addresses conflict the op is 0, if address 0,1 and 2 conflict op = 4 ..etc) But I am not getting the output when I simulate. (None of the if else condition is getting evaluated to 1 even though in that clock cycle there the signal has a value of 1.   I am not very well versed in verilog. I tried my best to debug the code. ( there is some logical error which I am not able to figure out) . If anyone could give some inputs on this it will be of great help. I have attached the code and its test bench.  Thanks.

[Altera_Forum]

"always @(posedge clock or write_addr_0 or write_addr_1 or write_addr_2 or write_addr_3)" 

This is weird. It's describing purely combinatory logic, as all the primary outputs are listed in the sensitivity list. So "posedge clk" is actually redundant. If you want sequential logic instead, leave just the "posedge clk".  That said, your comparisson logic looks broken. I really don't see why you bitwese comparison logic will produce 8'b0000_0001 when you have address collisions. Maybe it produces 8'b1111_1111 ?  But I suggest you use something simpler and let the synthesis tool sort it out. wire_01 = write_addr_0 != wire_addr1; // Produces a single bit result! ....

[Altera_Forum]

Hello,  

 Thanks for your input.. I cleaned up the code and it's working fine now. I made it a combinatory logic (without the clock). However I am facing an issue. 1) All the addresses pass through this comparator and are written into the memory 2) In the next clock cycle when I want to read from the address that I wrote to, the output isn't coming that clock cycle, but the next clock cycle.  Eg:# 10 --> write to address 01  # 20 --> Read from address 01 ( I should have got the output here) But I am gettin the output at# 30...  I am unable to understand this extra cycle delay because the comparator being a combinational circuit has its output ready in the same clock cycle it gets its input. I tried bypassing the comparator in which case I got the read output in the correct clock cycle. I am not able to find an answer as to why write is taking 2 clock cycles when a address comparator is connected :( . I have not addded any registers beetween the address comparator and the memory.   Any help is greatly appreciated...