Altera FPGA ring oscillator low level implementation

[Altera_Forum]

Hi all, 

 I'm a student working on a summer research project. I've been stuck on the same problem for some time now and would greatly appreciate any help.  Software/Hardware: Quartus II software to connect to an Altera DE2 board.  High level idea of project: Test for process variation of different chips.  Chip Overview: Chips consists of lots of LABs. Each LAB has 32 LEs. LEs are either LUTs or Flip Flops.  Implementation: Using VHDL, program ring oscillators. A ring oscillator consists of 4 buffers followed by an inverter. The low level of the chip consists of various LUTs. LUTs are capable of implementing any logical function. Thus program strings of ring oscillators by instantiating the LUTs as buffers or inverters as appropriate to create multiple ring oscillators on the chip.  After the program runs various time delays will be obtained which can be used to draw conclusions regarding process variation of the chip.  Problem: How to actually instantiate these elements (buffers and inverters) on the LUTs of the chip. I have tried various methods via the chip planner and assignment editor but I continually get the following warning:  Warning: Ignored locations or region assignments to the following nodes Warning: Node "ring_osc:\GEN_RO:0:XILINX_RO|inv_lut_out" is assigned to location or region, but does not exist in design  I need to know how to actually take the code and make instances of it on the LUTs of the chip.  Any help is greatly appreciated. Thank you.  pbryzek@ucla.edu  Paul

[Altera_Forum]

The nominal delays of inidividual LUT inputs are displayed in the Quartus Resource Property Editor. Routing delays are different between intra-LAB local interconnects and global inter-LAB routes.