Altera Monitor Program compile errors

[Altera_Forum]

I have followed the suggestion, re-installing my NIOS II EDS and Quartus II 9.0 to another path which contains no space. Then I tried to compile and load the c file again, I got the following new errors...please help have a look at it~ i am getting crazy~~ 

 p.s. I am trying to build a simple sopc following the tutorial document in cyclone II disk; I am using a different software version (9.0) with the one used in the tutorial (5.0), does this matter? it is claimed in the tutorial that this doesn't matter though.  Thank you~  nios2-elf-gcc -g -o1 -ffunction-sections -fverbose-asm -fno-inline -mno-cache-volatile -mno-hw-mulx -mno-hw-mul -mno-hw-div -id:/fyp_extra/nios2eds/components/altera_nios2/hal/inc -dsystem_bus_width=32 -dalt_single_threaded -d_jtag_uart_base=0x00003020 -wl,--defsym -wl,nasys_stack_top=0x2000 -wl,--defsym -wl,nasys_program_mem=0x1000 -wl,--defsym -wl,nasys_data_mem=0x1000 -wl,--section-start -wl,.exceptions=0x1020 -wl,--section-start -wl,.reset=0x1000 -wl,--script=d:/fyp_extra/nios2eds/bin/monitor/build/nios_cpp_build.ld -o d:/fyp_extra/sopc_builder_tutorial/app_software/lights.elf d:/fyp_extra/sopc_builder_tutorial/app_software/lights.c d:/fyp_extra/nios2eds/bin/monitor/lib/jtag_uart.c  d:/fyp_extra/sopc_builder_tutorial/app_software/lights.c: in function `main': d:/fyp_extra/sopc_builder_tutorial/app_software/lights.c:4: warning: return type of 'main' is not `int' d:/fyp_extra/sopc_builder_tutorial/app_software/lights.c:6:2: warning: no newline at end of file elf generated at d:\fyp_extra\sopc_builder_tutorial\app_software\lights.elf. nios2-elf-objcopy -o srec d:/fyp_extra/sopc_builder_tutorial/app_software/lights.elf d:/fyp_extra/sopc_builder_tutorial/app_software/lights.srec  srec generated at d:\fyp_extra\sopc_builder_tutorial\app_software\lights.srec. using cable "usb-blaster [usb-0]", device 1, instance 0x00 resetting and pausing target processor: failed leaving target processor paused

[Altera_Forum]

Did you configure the FPGA board first, with the Quartus programmer?

[Altera_Forum]

--- Quote Start ---  Did you configure the FPGA board first, with the Quartus programmer?  --- Quote End ---    Hi, yes I did program the FPGA Cyclone II first, using the generated file light_time_limit.sof (it is though strange that why is there a "_time_limit" at the back of the file since my project name is just "light"). Is it due to the abnormal .sof file?  I am using the manual which is written for Quartus II 5.0; however, I am using Quartus II 9.0, it is said the any version higher than 5.0 should work properly. But there are several difference indeed, I am wondering if it is because of the different versions of software that I am using?   thank you

[Altera_Forum]

The time_limit in the sof file name means that you don't have the licenses for every IP block you use in the design. I assume that it is the Nios processor. 

You are therefore in Opencore tethered evaluation mode, and it is important to: - keep the USB blaster connected to your board - keep the Opencore alert window open. I don't remember the exact text on the window, but basically it opens just after you configure the board, and says that you are evaluating Opencore plus IPs. do not click on "cancel"! Just run the IDE and dowload the software. If you click on cancel, it will stop all the demo IPs in the FPGA and this could explain your error message.

[Altera_Forum]

--- Quote Start ---  The time_limit in the sof file name means that you don't have the licenses for every IP block you use in the design. I assume that it is the Nios processor. You are therefore in Opencore tethered evaluation mode, and it is important to: - keep the USB blaster connected to your board - keep the Opencore alert window open. I don't remember the exact text on the window, but basically it opens just after you configure the board, and says that you are evaluating Opencore plus IPs. do not click on "cancel"! Just run the IDE and dowload the software. If you click on cancel, it will stop all the demo IPs in the FPGA and this could explain your error message.  --- Quote End ---    Hi, Daixiwen,  Thanks very much for the information. now i can successfully load the lights.c into the board, then I clicked the "action-->continue", however, the LEDs didn't react at all! The program is as follows: # define switches (volatile char *) 0x0001800# define leds (char *) 0x0001810 void main() { while (1) *leds = *switches; }  The c program is supposed to control the corresponding LEDs... Seems the loading was free of any errors, what could the problem be?  Thanks