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Valued Contributor III
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Altera Soft LVDS Megawizard Plugin issue

Hi all! 

 

I have an issue with Soft LVDS Megawizard Plugin. I am using Quartus 17.1.1 on Ubuntu 16.04 x86_64 machine. 

 

I am trying to get LVDS signal transmission with 7 bits per clock at 400 Mbps with outclock phase shifted. 

 

At first attempt I got unexpected coreclock frequency: 28.57 instead of expected 57.14. After a few experiments I have figured out that I get correct clock frequency until I change phase shift in the GUI. 

 

Here are settings I used without phase shift: 

https://alteraforum.com/forum/attachment.php?attachmentid=15443&stc=1  

https://alteraforum.com/forum/attachment.php?attachmentid=15444&stc=1  

https://alteraforum.com/forum/attachment.php?attachmentid=15445&stc=1  

 

With GUI settings I got following pll parameters (at lvds4_0002.v file): 

defparam lvds_tx_pll.clk0_divide_by = 1, lvds_tx_pll.clk0_multiply_by = 4, lvds_tx_pll.clk0_phase_shift = "-1250", lvds_tx_pll.clk1_divide_by = 7, lvds_tx_pll.clk1_multiply_by = 4, lvds_tx_pll.clk1_phase_shift = "-1250", lvds_tx_pll.clk2_divide_by = 7, lvds_tx_pll.clk2_multiply_by = 8, lvds_tx_pll.clk2_phase_shift = "-1250", lvds_tx_pll.inclk0_input_frequency = 20000, lvds_tx_pll.operation_mode = "normal", lvds_tx_pll.self_reset_on_loss_lock = "off", lvds_tx_pll.lpm_type = "fiftyfivenm_pll"; assign fast_clock = wire_lvds_tx_pll_clk, h_input = {wire_shift_reg24_shiftout}, l_input = {wire_shift_reg23_shiftout}, load_signal = dffe11, out_clock = wire_lvds_tx_pll_clk, outclk_load_signal = dffe22, slow_clock = wire_lvds_tx_pll_clk, tx_align_wire = {h_sync_b, l_sync_a}, tx_coreclock = txcoreclock_wire, tx_in_wire = tx_align_wire, tx_locked = (wire_lvds_tx_pll_locked & pll_lock_sync), tx_out = wire_ddio_out_dataout, tx_outclock = wire_outclock_ddio_dataout, txcoreclock_wire = wire_lvds_tx_pll_clk, w_reset = pll_areset;  

 

With input clock of 50MHz to PLL code above gets tx_coreclock = 8/7*50MHz = 57.14 MHz 

 

But if I introduce phase shift like I got following: 

https://alteraforum.com/forum/attachment.php?attachmentid=15446&stc=1  

 

defparam lvds_tx_pll.clk0_divide_by = 1, lvds_tx_pll.clk0_multiply_by = 4, lvds_tx_pll.clk0_phase_shift = "-1250", lvds_tx_pll.clk1_divide_by = 1, lvds_tx_pll.clk1_multiply_by = 4, lvds_tx_pll.clk1_phase_shift = "-1225", lvds_tx_pll.clk2_divide_by = 7, lvds_tx_pll.clk2_multiply_by = 4, lvds_tx_pll.clk2_phase_shift = "-1250", lvds_tx_pll.clk3_divide_by = 7, lvds_tx_pll.clk3_multiply_by = 4, lvds_tx_pll.clk3_phase_shift = "-1225", lvds_tx_pll.inclk0_input_frequency = 20000, lvds_tx_pll.operation_mode = "normal", lvds_tx_pll.self_reset_on_loss_lock = "off", lvds_tx_pll.lpm_type = "fiftyfivenm_pll"; assign fast_clock = wire_lvds_tx_pll_clk, h_input = {wire_shift_reg24_shiftout}, l_input = {wire_shift_reg23_shiftout}, load_signal = dffe11, out_clock = wire_lvds_tx_pll_clk, outclk_load_signal = dffe22, phase_shifted_slow_clock = wire_lvds_tx_pll_clk, slow_clock = wire_lvds_tx_pll_clk, tx_align_wire = {h_sync_b, l_sync_a}, tx_coreclock = txcoreclock_wire, tx_in_wire = tx_align_wire, tx_locked = (wire_lvds_tx_pll_locked & pll_lock_sync), tx_out = wire_ddio_out_dataout, tx_outclock = wire_outclock_ddio_dataout, txcoreclock_wire = wire_lvds_tx_pll_clk, w_reset = pll_areset;  

 

With input clock of 50MHz to PLL code above gets tx_coreclock = 4/7*50MHz = 28.57 MHz 

 

Is it a bug or I did something wrong?
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