Alternative to LPM_ROM needed

[Altera_Forum]

Helhlo everyone, 

 I am trying to implement a ROM with a slightly different behavior than the LPM_ROM from Altera. It should also have a memory initialization file. I have huge problems getting it to work. None of the textio functions are being executed by Quartus. Is there any way in Quartus to read a memory initialization file in a user-created entity?

[Altera_Forum]

You can have a look at this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf), on pages 14-33 and over. It looks like there is a way to read an initialization file in Verilog, but not in VHDL. You'll probably have to write the whole contents as an VHDL array, as described on example 14-30. 

(as a sidenote, srecord (http://srecord.sourceforge.net/) is a tool that can convert from and to lots of different EEPROM formats, and it can generate a VHDL table for you from a .hex or .mif file)

[Altera_Forum]

In what way do you want different behaviour? If you do things that LPM rom cannot then you run the risk of not inferring ram blocks. 

 It is very annoying that you cannot use textio to initialise a memory (Xilinx will). Raise a support request with Altera and maybe one day they'll implement it. Any chance you could use a initialisation function to generate the values?  You can also use the "ram_init_file" synthesis attribute to get the memory contents, while also using textio to initialise the ram for simulation: http://quartushelp.altera.com/11.1/mergedprojects/hdl/vhdl/vhdl_file_dir_ram_init.htm

[Altera_Forum]

--- Quote Start ---  Helhlo everyone,  I am trying to implement a ROM with a slightly different behavior than the LPM_ROM from Altera. It should also have a memory initialization file. I have huge problems getting it to work. None of the textio functions are being executed by Quartus. Is there any way in Quartus to read a memory initialization file in a user-created entity?  --- Quote End ---     It works, thank you so much. I couldn't figure it out for the life of me.

[Altera_Forum]

The following code works in Quartus and simulates correctly. I will download it to a DE1 board tmorrow to see if it works on the hardware. 

 module rom_verilog_mif (  input [3:0] addr_a,  input clk,  output reg [7:0] q_a );  reg [7:0] rom[0:15];  initial begin  $readmemh("memory.mif", rom); end  always @ (posedge clk) begin  q_a <= rom[addr_a]; end  endmodule

[Altera_Forum]

Your code looks like a normal LPM rom to me - what is different?

[Altera_Forum]

--- Quote Start ---  Your code looks like a normal LPM rom to me - what is different?  --- Quote End ---    Oh, this was just a test, now I can implement what I need - a triple port rom BTW.

[Altera_Forum]

A triple port rom will not map to the ram on the chip, so it will have to generate it from logic, probably take a long time to synthesis and take a hiddeous amount of logic. 

 WHy not just use a dual port and single port rom using the same mif file?

[Altera_Forum]

--- Quote Start ---  A triple port rom will not map to the ram on the chip, so it will have to generate it from logic, probably take a long time to synthesis and take a hiddeous amount of logic.  WHy not just use a dual port and single port rom using the same mif file?  --- Quote End ---    Oh, havent though of that. good idea. Thank you very much.