An array of constants / parameters

Altera_Forum · ‎06-26-2013

I have several constants that I want to concatenate and place into an array (reg / parameter?). That array will be compared to another array of the exact same size.


reg         setup_packet;
reg           byte0 = 8'h01;
parameter  getdevicedescriptor  =  {byte0 && byte1,
                                                word0, word1,
                                                byte2 && byte3
                                                };
if (setup_packet == getdevicedescriptor) status <= rejoice;
.....

I keep getting the following error and I just don't undertsand how to resolve the proper syntax. I don't really understand packed vs unpacked arrays. D;

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Error (10673): SystemVerilog error at usb_protocol.v(46): assignments to unpacked arrays must be aggregate expressions

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Altera_Forum · ‎06-26-2013

You can read this paper (http://www.mentor.com/products/fv/resources/overview/using-strong-types-in-your-systemverilog-design-and-verification-c953bc93-075a-4b67-9e03-aab28f5bf696)to help understand the difference between packed an unpacked types.

Some tools have difficulty understanding the difference between a concatenation of bits which is a packed vector versus an unpacked array assignment, both of which use the {value1,value2} syntax. You can put a ' in front of the {} to ensure that it is recognized as an assignment pattern. See section 10.10 of the LRM

But then the array assignment '{} would expect 9 unpacked array elements each 16 bits wide.

Altera_Forum · ‎06-26-2013

Yup, the ' fixed it. Yes, the number of bytes/words I typed wasn't the correct number (9), but I was just being lazy. Thanks!

Altera_Forum · ‎10-21-2014

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Yup, the ' fixed it. Yes, the number of bytes/words I typed wasn't the correct number (9), but I was just being lazy. Thanks!

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Adding ' It doesnt fix my problem.

I use the following line

parameter reg [7:0] LCD_CMDS [0:23] = '{8'h3C, 8'h0C, 8'h01, 8'h02, 8'h48, 8'h65, 8'h6C, 8'h6C, 8'h6F, 8'h20, 8'h46, 8'h72, 8'h6F, 8'h6D, 8'h20, 8'h44, 8'h69, 8'h67, 8'h69, 8'h6C, 8'h65, 8'h6E, 8'h74, 8'h18};

and it returns=> Error (10170): Verilog HDL syntax error at PmodCLP.v(75) near text "'"; expecting an operand

Need help..:)

-Fahmy

Altera_Forum · ‎10-21-2014

Your file compiled fine in ModelSim. Make sure you are compiling your file as SystemVerilog (use .sv extension).

Altera_Forum · ‎10-23-2014

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You file compiled fine in ModelSim. Make sure you are compiling your file as SystemVerilog.

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Thanks , it works with system verilog. All this while I was using .v.

-Fahmy