Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,442 Views

An issue about compiling the OpenCL to FPGA

Hi, 

 

I met an issue about compiling the OpenCL HelloWorld/Vector_add code to FPGA. 

 

Quartus Prime can offload the VHDL code into the FPGA board but the OpenCL SDK and compiler can not program to the FPGA board instead.  

 

[root@localhost vector_add]# aoc -v device/vector_add.cl -o bin/vector_add.aocx --board de5a_net_i2 --report 

aoc: Environment checks are completed successfully. 

You are now compiling the full flow!! 

aoc: Selected target board de5a_net_i2 

aoc: Running OpenCL parser.... 

/root/intelFPGA_pro/17.0/hld/board/de5a_net_i2/tests/vector_add/device/vector_add.cl:23:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance 

__kernel void vector_add(__global const float *x,  

/root/intelFPGA_pro/17.0/hld/board/de5a_net_i2/tests/vector_add/device/vector_add.cl:24:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance 

__global const float *y,  

2 warnings generated. 

aoc: OpenCL parser completed successfully. 

aoc: Compiling.... 

aoc: Linking with IP library ... 

Checking if memory usage is larger than 100% 

 

 

+--------------------------------------------------------------------+ 

; Estimated Resource Usage Summary ; 

+----------------------------------------+---------------------------+ 

; Resource + Usage ; 

+----------------------------------------+---------------------------+ 

; Logic utilization ; 19% ; 

; ALUTs ; 10% ; 

; Dedicated logic registers ; 10% ; 

; Memory blocks ; 11% ; 

; DSP blocks ; 5% ; 

+----------------------------------------+---------------------------; 

aoc: First stage compilation completed successfully. 

Error: Compiler Error, not able to generate hardware 

 

 

 

I set up all required driver/BSP (board supported package from Terasic)/env variables/libraries and followed the official manual carefully but still have this issue. 

 

[root@localhost vector_add]# aoc --list-boards 

Board list: 

de5a_net_i2 

 

But whlie running the aocl diagnose: 

 

 

[root@localhost vector_add]# aocl diagnose 

aocl diagnose: Running diagnose from /root/intelFPGA_pro/17.0/hld/board/de5a_net_i2/linux64/libexec 

aocl diagnose: failed 32 times. First error below: 

Vendor: Terasic 

 

 

Found no active device installed on the host machine. 

 

 

Please make sure to:  

1. Set the environment variable AOCL_BOARD_PACKAGE_ROOT to the correct board package. 

2. Install the driver from the selected board package. 

3. Properly install the device in the host machine. 

4. Configure the device with a supported OpenCL design. 

5. Reboot the machine if the PCI Express link failed. 

 

Configuration: 

FPGA board: Terasic De5a-Net FPGA with Arria 10 

Quartus Prime Pro Edition with OpenCL SDK 

 

All the manuals and drivers can be found here: 

https://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=231&no=970&partno=4 

 

 

 

A similar question in the forum but still didn't have solutions yet: 

https://alteraforum.com/forum/archive/index.php/t-45872.html 

 

I am looking for any helps/advise! Thank you so much! 

 

All the best, 

Jiawen
0 Kudos
12 Replies
Altera_Forum
Honored Contributor I
212 Views

OpenCL "compilation" has nothing to do with the diagnose script returning success or not. Your compilation is failing because you are using Quartus v17.0, while Terasic provides BSPs only for v16.0 and v16.1. You MUST use the same Quartus version as your BSP version. It is preferred to use the latest subversion (e.g. Quartus 16.0.2 with BSP v16.0 or Quartus v16.1.2 with BSP v16.1) unless the manufacturer specifically instructs you use a specific subversion. 

 

Your diagnose script is failing since you either do not have the board correctly installed on your machine, or it is not being detected correctly. Terasic has detailed instructions of the steps you need to take to install the board and the driver in their OpenCL manual. Make sure you are using a supported OS (e.g. Ubuntu is NOT supported).
Altera_Forum
Honored Contributor I
212 Views

Hi HRZ, 

 

Thank you! But I still had an issue while I installed the Driver. I reinstalled the system with CentOS 7.2(the one in the manual) and the Quartus Prime 16.1 with the same version of BSP (Board Support Passage). The issue is as below: 

 

[root@localhost PCIe_Driver]# pwd 

/root/Downloads/DE5a_Net_PCIe/PCIe_SW_KIT/Linux/PCIe_Driver 

[root@localhost PCIe_Driver]# make 

make -C /lib/modules/3.10.0-327.el7.x86_64/build M=/root/Downloads/DE5a_Net_PCIe/PCIe_SW_KIT/Linux/PCIe_Driver 

make[1]: Entering directory `/usr/src/kernels/3.10.0-693.2.2.el7.x86_64' 

Building modules, stage 2. 

MODPOST 1 modules 

make[1]: Leaving directory `/usr/src/kernels/3.10.0-693.2.2.el7.x86_64' 

[root@localhost PCIe_Driver]# sh load_driver  

insmod: ERROR: could not insert module ./altera_pcie.ko: Unknown symbol in module 

 

I followed the instruction step by step and used the same CentOS7.2 as the manual. 

 

Does anyone have any ideas how to solve it? 

 

Thank you so much for your time! 

 

Jiawen 

 

 

 

 

--- Quote Start ---  

OpenCL "compilation" has nothing to do with the diagnose script returning success or not. Your compilation is failing because you are using Quartus v17.0, while Terasic provides BSPs only for v16.0 and v16.1. You MUST use the same Quartus version as your BSP version. It is preferred to use the latest subversion (e.g. Quartus 16.0.2 with BSP v16.0 or Quartus v16.1.2 with BSP v16.1) unless the manufacturer specifically instructs you use a specific subversion. 

 

Your diagnose script is failing since you either do not have the board correctly installed on your machine, or it is not being detected correctly. Terasic has detailed instructions of the steps you need to take to install the board and the driver in their OpenCL manual. Make sure you are using a supported OS (e.g. Ubuntu is NOT supported). 

--- Quote End ---  

Altera_Forum
Honored Contributor I
212 Views

You are not supposed to compile and load the driver manually. Just make sure AOCL_BOARD_PACKAGE_ROOT points to your BSP and run "aocl install". That will compile and load the PCI-E driver automatically. 

These steps are described in Terasic's document.
Altera_Forum
Honored Contributor I
212 Views

Hi HRZ, 

 

Thank you so much for your quick reply! 

 

I ignored the driver from Teraric and installed the driver from OpenCL SDK by "aocl install". I can install the driver successfully: 

 

[root@localhost vector_add]# lsmod 

Module Size Used by 

aclpci_de5a_net_i2_drv 36672 0 

 

But while I run the "aocl diagnose", there is still an error: 

 

 

[root@localhost vector_add]# aocl diagnose 

aocl diagnose: Running diagnose from /root/intelFPGA_pro/16.1/hld/board/de5a_net_i2/linux64/libexec 

aocl diagnose: failed 32 times. First error below: 

Vendor: Terasic 

MMD INFO : [aclde5a_net_i20] PCIe-to-fabric read test failed, read 0xffffffff after 1 attempts 

Phys Dev Name Status Information 

aclde5a_net_i20Failed Board name not available. 

Failed initial tests, so not working as expected. 

Please try again after reprogramming the device. 

 

 

Found no active device installed on the host machine. 

 

 

Please make sure to:  

1. Set the environment variable AOCL_BOARD_PACKAGE_ROOT to the correct board package. 

2. Install the driver from the selected board package. 

3. Properly install the device in the host machine. 

4. Configure the device with a supported OpenCL design. 

5. Reboot the machine if the PCI Express link failed. 

 

 

 

DIAGNOSTIC_FAILED 

 

Used lspci to check device and only saw: 

 

 

[root@localhost vector_add]# lspci 

 

01:00.0 Processing accelerators: Altera Corporation Device 2494 (rev ff) 

 

 

The problem now is that, while I program the helloworld example as the manual into the FPGA, it shows that: 

 

 

[root@localhost bin]# aocl program aclde5a_net_i20 hello_world.aocx 

aocl program: Running program from /root/intelFPGA_pro/16.1/hld/board/de5a_net_i2/linux64/libexec 

MMD INFO : [aclde5a_net_i20] PCIe-to-fabric read test failed, read 0xffffffff after 1 attempts 

Failed clGetDeviceIDs. 

Error code: -1 

Failed clGetDeviceIDs. 

Error code: -30 

Failed to find requested device aclde5a_net_i20 from 0 devices 

 

aocl program: Program failed. 

 

 

 

I am still not sure whether it's the problem of the driver or not.  

 

Do you have any idea/solution for this issue? Thank you so much, HRZ. 

 

Jiawen 

 

 

--- Quote Start ---  

You are not supposed to compile and load the driver manually. Just make sure AOCL_BOARD_PACKAGE_ROOT points to your BSP and run "aocl install". That will compile and load the PCI-E driver automatically. 

These steps are described in Terasic's document. 

--- Quote End ---  

Altera_Forum
Honored Contributor I
212 Views

The driver includes board-specific PCI-E timing. You MUST use the driver provided by Terasic. I urge you to read and follow the steps mentioned in Terasic's "OpenCL User Manual" for that board.

Altera_Forum
Honored Contributor I
212 Views

Hi HRZ, 

 

 

Actually, I followed the steps of both Terasic's "OpenCL User Manual" and the Terasic's "Board User Manual" for the board driver. The driver I used is from Terasic. 

 

 

The driver seems installed successfully since I can see it in "lsmod". But I am not sure whether the issue of "aocl diagnose" and "aocl program are from driver or not. 

 

 

Do you have any ideas for the error of "aocl diagnose" and "aocl program"? 

 

 

Thank you. 

 

 

Jiawen 

 

 

 

--- Quote Start ---  

The driver includes board-specific PCI-E timing. You MUST use the driver provided by Terasic. I urge you to read and follow the steps mentioned in Terasic's "OpenCL User Manual" for that board. 

--- Quote End ---  

Altera_Forum
Honored Contributor I
212 Views

The diagnose script has the following summary for the necessary steps: 

 

1. Set the environment variable AOCL_BOARD_PACKAGE_ROOT to the correct board package. 2. Install the driver from the selected board package. 3. Properly install the device in the host machine. 4. Configure the device with a supported OpenCL design. 5. Reboot the machine if the PCI Express link failed. 

 

The script will fail if any of these steps are not performed correctly, and you cannot use the board via OpenCL. If you performed all the steps correctly and the script still fails, I recommend contacting Terasic directly.
Altera_Forum
Honored Contributor I
212 Views

Thank you HRZ! 

 

I can offload the executable file into the FPGA board now and can run aocl diagnose successfully. 

 

However, I just run the execution file from the BSP of Altera and another issue is that while OpenCL SDK compiled the kernel code, it still can not generate the offloading executable file for FPGA even though we can offload the executable file for the FPGA: 

 

[root@localhost hello_world]# aoc -v device/hello_world.cl -o bin/hello_world.aocx --board de5a_net_i2 --report 

aoc: Environment checks are completed successfully. 

You are now compiling the full flow!! 

aoc: Selected target board de5a_net_i2 

aoc: Running OpenCL parser.... 

aoc: OpenCL parser completed successfully. 

aoc: Compiling.... 

aoc: Linking with IP library ... 

 

+--------------------------------------------------------------------+ 

; Estimated Resource Usage Summary ; 

+----------------------------------------+---------------------------+ 

; Resource + Usage ; 

+----------------------------------------+---------------------------+ 

; Logic utilization ; 19% ; 

; ALUTs ; 10% ; 

; Dedicated logic registers ; 10% ; 

; Memory blocks ; 10% ; 

; DSP blocks ; 5% ; 

+----------------------------------------+---------------------------; 

aoc: First stage compilation completed successfully. 

Error: Compiler Error, not able to generate hardware 

 

I followed the other thread in this forum: 

https://alteraforum.com/forum/showthread.php?t=55654 

https://www.alteraforum.com/forum/showthread.php?t=55176 

 

I tried the combination of vertion with upgrade as you mentioned in the threads above but still didn't work: 

1. Quartus Prime Pro 16.1.0 and OpenCL SDK 16.1.0 

2. Quartus Prime Pro 16.1.2 and OpenCL SDK 16.1.0 

3. Quartus Prime Pro 16.1.2 and OpenCL SDK 16.1.2 

 

The error in the log file "quartus_sh_compile.log" is as below: 

 

Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design. 

Error (15744): In atom 'board_inst|pcie|pcie|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_sd.inst_twentynm_hssi_pma_rx_sd' 

Error (15744): The settings must match one or more of these conditions: 

Error (15744): ( sup_mode == ENGINEERING_MODE ) OR ( prot_mode != PCIE_GEN3_RX ) OR ( sd_output_off == CLK_DIVRX_14 ) 

Error (15744): But the following assignments violate the above conditions: 

Error (15744): sup_mode = USER_MODE 

Error (15744): prot_mode = PCIE_GEN3_RX 

Error (15744): sd_output_off = CLK_DIVRX_6 

Error (18590): The imported netlist contains settings that are not supported by the current version of the software. Import using the --timing_analysis_mode option, which ignores the errors and allows Timing Analysis to be run. 

Error: design::import_design -file base.qdb -overwrite failed! 

Error (23031): Evaluation of Tcl script /root/intelFPGA_pro/16.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful 

Error: Quartus Prime Compiler Database Interface was unsuccessful. 11 errors, 0 warnings 

Error: Peak virtual memory: 4554 megabytes 

Error: Processing ended: Mon Sep 18 02:40:32 2017 

Error: Elapsed time: 00:16:10 

Error: Total CPU time (on all processors): 00:16:09 

 

 

Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful 

Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings 

Error: Peak virtual memory: 1179 megabytes 

Error: Processing ended: Mon Sep 18 02:40:34 2017 

Error: Elapsed time: 00:16:13 

Error: Total CPU time (on all processors): 00:16:11 

 

 

 

Does anyone have the similar experience or any solution/ideas for this issue?  

 

Thank you! 

 

Jiawen
Altera_Forum
Honored Contributor I
212 Views

Another user reported a similar issue here (http://www.alteraforum.com/forum/showthread.php?t=56531). This seems like a compatibility issue between the BSP and Quartus. If you are using Terasic's v16.1 BSP, I recommend contacting their support since their BSP could be broken.

Altera_Forum
Honored Contributor I
212 Views

Hi HRZ, 

 

I just received an email from Terasic. They told me that since I can offload the executable file into the FPGA board, it's no problem with the BSP and driver. They said it's most possible that the OpenCL aoc compiler or the Quartus Prime have some bugs for compiling the OpenCL kernel program into the executable file. Do you have any solutions/ideas with that? Or do you have other patch for Quartus Prime 16.1.2 for this? 

 

Thank you!
Altera_Forum
Honored Contributor I
212 Views

So they put the blame on Altera, that is convenient for them. I have been using the same version of Quartus (16.1.2) with another manufacturer's board and BSP and I have no problems whatsoever. Being able to program the FPGA does not prove their BSP is working correctly, it just shows that their PCI-E driver is working. I am afraid I have no other solutions for you. You can contact Altera instead and show them your compilation log and ask what is wrong, but they will likely tell you to go contact Terasic because this is most likely a problem with Terasic's BSP.

Altera_Forum
Honored Contributor I
212 Views

I just tried Terasic's 16.1 DE5A-Net BSP (both I2 and E1) with Quartus v16.1.2 on my own environment on a kernel I had previously compiled successfully using another manufacturer's BSP. I got the exact same compilation error as reported by jm1ppqpotss with both of the BSPs. The compilation fails while importing the static region from the BSP. The problem is DEFINITELY from the BSP and not Quartus. Their Windows BSP might work, but their Linux BSP is definitely broken.