Another beginners question

[Altera_Forum]

Being new to FPGA's ( started yesterday ) when I was given an Altera DE2-115  

I find I keep coming up with lots of questions that I dont know the answer to  I have been reading all I can in the way of tutorials etc and I tried entering a simple example that I found online  to make a 2 way switch ( basically a 2 input exclusive or gate)  I built it first in the schematic design method as it sounded easier and it worked fine  I then built it using VHDL and that also works great but that raised my first question which is....  if I build it using Schematic design , will Quartus let me convert it into a VHDL file that I can look at to see how it would be written that way and vice versa if I write it using VHDL can Quartus convert it into a schematic design that I can view to see if its what I intended ?  and if that is possible how do I do it ?  I have lots of other questions but I wont be greedy so I will ask just one more for now   Being new to FPGA's I have installed the latest free edition of Quartus II which is V15.0.0 64 bit  I had down loaded a tutorial called " my first NIOS II for Altera DE2-115 but when I tried to follow it  it told me to open Tools/SOPC Builder which my version of Qaurtus doesnt have . I looked online for answers and it seems SOPC Builder no longer appears in the newer versions of Quartus and to use QSys instead  so does any one know if there is an equivelent to "My First Nios II " as a tutorial but written for Qsys rather than SOPC  Regards Don

[Altera_Forum]

Hi Don, 

 Don't start with Qsys, start with straight VHDL or Verilog. Do not even bother with schematics, start with an HDL.  An FPGA design consists of;  1. Your hardware design (in VHDL or Verilog)  2. Your device assignment (the FPGA you are using)  3. Your pin assignments (CRITICALLY IMPORTANT)  4. Your timing assignments  You can get away with HDL and pin assignments to start with, and Quartus will generate some warning messages about a missing clock constraint. You can safely ignore that for beginner designs, but not for long!  Start out by simply routing the switches to the LEDs, eg., your HDL will look something like   -- Entity (VHDL) or Module (Verilog) definition (ports on the component) -- Switch inputs -- LED outputs -- Body of the code with ... leds <= switches; -- VHDL assign leds = switches; -- Verilog   I deliberately left out the syntax details. You can figure those out.  Hint: the Quartus editor has templates that you can insert and then fill in the details.  Use the assignments editor to create the pin constraints.  When you synthesize the design, check the .pin file has pin assignments that matches the DE2-115.  If you are worried you will damage your board, create a .qar file, and email it to me (use my Altera Forum name), and I'll take a look at the design.  Cheers. Dave

[Altera_Forum]

I would add that you do make a schematic design, but on paper. First think about the hardware you want, then write HDL to make it.

[Altera_Forum]

--- Quote Start ---  I would add that you do make a schematic design, but on paper. First think about the hardware you want, then write HDL to make it.  --- Quote End ---   That is a good point.  If you cannot draw a block diagram, or the block diagram looks too complicated, then often your design is too complicated.  I often apply this philosophy to my state machine designs; I get them working, then as I document them using Algorithmic State Machine (ASM) charts, I often realize that I can simplify them. (Often I can simply copy a working design and modify it too, or generalize it to cover a new use case).  Don - there are plenty of resources on this page (they're not all beginner level, but you can at least see examples of code and documentation).  https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html  Cheers, Dave

[Altera_Forum]

Hi Dave  

 Thanks for the reply  Basically what you suggest is what I have been doing  I decided at the beginning to use VHDL rather than verilog and used this bit of code   library ieee; use ieee.std_logic_1164.all; entity light2 is port (x1, x2 : in std_logic; f : out std_logic); end light2; architecture LogicFunction of light2 is begin f<= (x1 and not x2) or ( not x1 and x2); END LogicFunction ;   But first I did it in Schematic which for a simple code like this was uneccesary but had it been more complex  then for a beginner it would be easier. The reason I asked my question , which I think you missed was to ask if it is possible to get VHDL from a schematic or Schematic from VHDL so that should I wish to to code something that was more complex I could first do it in schematic and then if its possible convert that to VHDL so that I could see what I should actually write in VHDL code and conversely if I saw someone elses code in VHDL that was beyond my understanding then if its possible to convert it to a schematic I might better understand what is going on .  So is it possible, will Quatus II convert VHDL to schematic or the other way round schematic to VHDL ?  Regards Don     --- Quote Start ---  Hi Don,  Don't start with Qsys, start with straight VHDL or Verilog. Do not even bother with schematics, start with an HDL.  An FPGA design consists of;  1. Your hardware design (in VHDL or Verilog)  2. Your device assignment (the FPGA you are using)  3. Your pin assignments (CRITICALLY IMPORTANT)  4. Your timing assignments  You can get away with HDL and pin assignments to start with, and Quartus will generate some warning messages about a missing clock constraint. You can safely ignore that for beginner designs, but not for long!  Start out by simply routing the switches to the LEDs, eg., your HDL will look something like   -- Entity (VHDL) or Module (Verilog) definition (ports on the component) -- Switch inputs -- LED outputs -- Body of the code with ... leds <= switches; -- VHDL assign leds = switches; -- Verilog   I deliberately left out the syntax details. You can figure those out.  Hint: the Quartus editor has templates that you can insert and then fill in the details.  Use the assignments editor to create the pin constraints.  When you synthesize the design, check the .pin file has pin assignments that matches the DE2-115.  If you are worried you will damage your board, create a .qar file, and email it to me (use my Altera Forum name), and I'll take a look at the design.  Cheers. Dave  --- Quote End ---  

[Altera_Forum]

If you go to tools -> netlist veiwer -> RTL view that will give you a schematic view of the design at the RTL level. The post map viewer will give you a view of the design at the primitives level (luts and registers) - these are not the same as the schematic entry mode. 

Quartus can convert schematics that you draw to VHDL - but I dont think you'll like reading the VHDL that is generates much. It is only really meant for simulation.  But as other have said, before you write any code, you need to draw your schematic on paper. When you get used to this, and you can think in schematics, then you can move more freely with the code. But with any design, the documentation should break the design down as much as possible before any code is written.

[Altera_Forum]

Thanks for all the replies .  

I can see the sense in what you are all saying , especially about getting it down on paper first so I can see where I am going I did try what Tricky said using tools/netlist viewer/RTL and yes it did give me a view of a schematic that might let me better understand someone elses code  and I did try going the otherway converting schematic to VHDL but the code was a bit weird , it put in lots of lines about synthesized wires , which I hadnt used in my VHDL code  I think the hardest part for me right now is thinking of something to try to code that is simple enough for a raw beginner like me , but  interesting enough for me to want to do it  Don

[Altera_Forum]

At my university we had classes in VHDL. We first started by making a sevensegment decoder. The switches were inputs, the sevensegs, what else, were outputs. This was then expanded to a four-sevenseg decoder to start on portmapping. Then we made stuff like a comparator, multiplexer etc. I beleve we also did a simple version of a "knightrider effect". A shift register that is connected to the leds of the board and it shifts one bit over the leds bouncing it from the edges. These shouldn't be too hard if you take it step by step.

[Altera_Forum]

--- Quote Start ---  Thanks for all the replies .  I can see the sense in what you are all saying , especially about getting it down on paper first so I can see where I am going I did try what Tricky said using tools/netlist viewer/RTL and yes it did give me a view of a schematic that might let me better understand someone elses code  and I did try going the otherway converting schematic to VHDL but the code was a bit weird , it put in lots of lines about synthesized wires , which I hadnt used in my VHDL code  I think the hardest part for me right now is thinking of something to try to code that is simple enough for a raw beginner like me , but  interesting enough for me to want to do it  Don  --- Quote End ---    This "synthesised_wires" are just signals to connect the things together. Auto Generated code is generally a mess and not very nice to read, so dont bother (write it yourself) Altera has plenty of guidelines how to write code to infer all the primitives in different modes - have a read of the HDL coding guide (section 12): https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf  My first HDL project was my final year project. We had been given an "idealised" CPU instruction set the year before, and the project was to implement a CPU that used it. It was a simple fixed width instruction based, with very little in the way of complicated instructions- load A, load B - Add A, B, Jump etc. But it got me understanding HDL (with a lot of help from a PhD friend).

[Altera_Forum]

--- Quote Start ---    https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html    --- Quote End ---    This is a great link! Very informative!

[Altera_Forum]

--- Quote Start ---  This is a great link! Very informative!  --- Quote End ---    I am sure you are right but its a little ( make that a lot ) too advanced for me right now , but I have bookmarked it for the future and am always glad of links to stuff that will help me out so allthough I am not able to use this link yet , hopefully one day I will be   I have only started with FPGA for about 2 days now and most of that time has been spent , loading Quartus II V 15 software onto my PC , arranging directories to store books, manuals, Tutorials etc . And the rest of the time , watching online tutorials , printing out usefull charts ( like the pin assignments for me DE2-115 board ) It doesnt help either that I am now a pensioner and so things dont sink in my brain as quick as they did when younger. Programming has not been something I have done for a living  I am just an electronics enthusiast thats hoping to pick up enough about FPGAs to make it interesting . Its also a way to keep my brain active   My first mistake was downloading every tutorial I could find . only to find some were for Quartus II versions prior to 15 and sometimes they have things no longer found in the newer version or has been replaced  by a better alternative . If I were more knowlegable I am sure I could work out ways around this but being a raw beginner I cant so I have now only kept the tutorials for version 15 second problem was some tutorials were using Verilog and some VHDL . Again if I was younger or more experienced in FPGAs I might have a chance at learning two languages , but for me one is more than enough to cope with and so I settled on VHDL . From what I read this is what most europeans use.  So any help , links , tips tutorials or ideas for something to try to code ( that are suitable for a complete beginner and use VHDL on Quartus II V 15) I would be glad to receive them   I know its only easy but for my first project I am going to try to use the switches and leds on the DE2-115 to simulate simple gates , AND OR NAND NOR XOR etc  if nothing else it will start to teach me the correct syntax for writing entities and architectures and to find my way around the Quartus GUI  Regards Don

[Altera_Forum]

Hi Don, 

 You're on the right track. Start simple and once you understand your first few example designs, you can then read the more complicated material. Your first task is to get to know the tools.  You posted some VHDL. Did you try synthesizing it and looking at the RTL view? How about pin assignments, did you make some of those? Once you have a project that synthesizes, look at the .pin file, and if it looks ok, download it to your board.  The next project after that would be to make a blinking LED. Then make a count on the hex displays. At that point you'll feel a lot more comfortable with the synthesis tool.  Then you can take a look at a more complicated design, and simulation (using Modelsim).  Cheers, Dave

[Altera_Forum]

Thanks for the encouragement Dave  

Yes I did synthesize the code I uploaded and assigned some pins to it and it eventually did as it should . I say eventually because when I tried to synthesize it I got a warning telling me that Error: The core supply voltage value of '1.0V' is illegal for the currently selected part. but it seems thats a known problem with Quartus 9.1 SP2 as its in the DE2-115 FAQs and they give a work around I have since changed from Quartus II v9.1 SP2 to V15 and it doesnt do that any more . The circuit was for a 2 way light switch, the sort of thing you would have on the stairs  and it operated as a simple xor gate . in as much as if the 2 switches were set both up  or both down the light was off , but one up and one down the light came on I wrote the code first using the schematic and then later wrote it in VHDL and both worked  Although the schematic method was easier for that small circuit I can see that in a big circuit it might get out of hand  I spent most of today printing out crib sheets of how to write an entity and architecture showing where you put in semi colons and where not to so as to keep the syntax correct I also printed out a list of pin numbers for the switches, Leds and 7 segments so I dont have to keep hunting through the manual to find them  Making a blinking LED as you suggest should be a fun project and also playing with the 7 segments   I was just trying to think what the best way to blink a LED would be . I suppose I could devide a 50Mhz clock by 2 about 25 times with a lot of D flip flops and that would give me a flash rate of about 1.5 Hz  or I could just tell it to turn on wait for a set time and then turn off and wait again then loop to the top and start again or maybe I can get a PLL to give me the frequency I want ? I dont know . I never have used a PLL yet  Oh well fun times ahead trying to find out  Speak again soon Don

[Altera_Forum]

--- Quote Start ---  Thanks for the encouragement  --- Quote End ---   Sometimes its all we need, right? :)   Glad to hear you are using Quartus 15.0. Typically you want to stick with the latest version if you can. Fortunately the DE2-115 uses a Cyclone IV so you can work with v15.0.     --- Quote Start ---   I wrote the code first using the schematic and then later wrote it in VHDL and both worked  Although the schematic method was easier for that small circuit I can see that in a big circuit it might get out of hand  --- Quote End ---   When you get to writing a 7-segment decoder, you'll start to appreciate the beauty of an HDL language relative to a schematic.    --- Quote Start ---   I spent most of today printing out crib sheets of how to write an entity and architecture showing where you put in semi colons and where not to so as to keep the syntax correct   --- Quote End ---   The Quartus editor templates can help you out there too, by giving you a starting point.    --- Quote Start ---   I also printed out a list of pin numbers for the switches, Leds and 7 segments so I dont have to keep hunting through the manual to find them   --- Quote End ---   You can use Tcl to automatically assign the pin numbers. That way you get it right once, and use the right values for all subsequent projects.  Once you have got your 7-segment decoder working and counting, then I'd say you're ready to learn some Tcl scripting, I'll take your code and automate the creation of a project for you.    --- Quote Start ---   Making a blinking LED as you suggest should be a fun project and also playing with the 7 segments    --- Quote End ---   It is indeed gratifying :)     --- Quote Start ---   I was just trying to think what the best way to blink a LED would be .   --- Quote End ---   Create a counter and use the MSB of the counter to drive the LED. The width of the counter is as many bits as is needed to blink at the rate you desire, eg., clock frequency x 0.5s for a half-second blink period.  Then when you get to the 7-segment display, you send the 4 MSBs of that counter (or one that is slightly wider) to a 4-input to 7-segment output decoder.  Take a shot at it, and then I'll show you some examples that use generics and floating-point math to calculate the bit-widths (the pre-processor does the math, rather than synthesizing it into hardware).  Cheers, Dave

[Altera_Forum]

The pin assignments can be doneein another way. One of the files from the resources link on the Altera (or was it Terasic) page is a .csv file with the assignments. In your project go to settings->import assignments, and you should be able to get all the pins in the pin planner without having to script it yourself.

[Altera_Forum]

Hi Dave  

I went online to find examples so I could see what they are doing and hopefully cobble some bits together to make mine  So far I had only used STD_LOGIC_1164 but looking online the example that looked most usefull used IEEE.Numeric.STD From this I think they used " Unsigned " .  To be honest I dont understand why they used it but gave it a go anyway   I made my entity with a clk input and q output (27 downto 0) for the architecture I declared a signal called count and told it  on the rising edge of clk to assign the value of " count + 1 " to the present value of "count" then told it that "q" is assigned this new updated value of "count"  It took a few goes to get the syntax right so that everything compiled ok  but eventually got there  I assigned the pins so that the 50Mhz clk went to the clk input and I chose several tries at which "q" I used for the output till I found that q(24) seemed a good speed   I programed it to the DE2-115 and it did exactly as I wanted , flashing the first LED on and off , but for some reason there are random characters running across the LCD screen too, I dont know why as I have assigned no other pins ?  Once this was working I made a second copy of the program but this time assigned the outputs Q24-Q27 to four LEDs and instead of feeding pulses from the  50Mhz clock I used one of the push buttons , so that it gave a binary count on the LEDs that increased with each push of the button  It skipped now and again but I expect that is just switch bounce  I have been thinking about the 7 segment display and decoding it  I can see that if I take my 4 bit binary output from this last design that I could possibly work out how to decode it using case statements. If I make it have (3 downto 0) for the 4 inputs and (6 downto 0) for the 7 outputs to the segments  What I am not sure of is can I make this second entity and architecture for the decoder in the same file as the counter section or can I only have one entity per VHD file  in which case I am not sure how I make one file talk to the other , thats something else I must read up on  anyway , this was my code that I wrote . It probably isnt elegant or efficient , but it does work  Library IEEE; Use IEEE.numeric_std.all; use IEEE.STD_Logic_1164.all; entity Led_Blink is port ( -- Input ports clk : in STD_Logic; -- Output ports q : out unsigned (27 downto 0) ); end Led_Blink; architecture Counter of Led_Blink is signal count : unsigned(27 downto 0); begin process (clk) begin if rising_edge (clk) then count <= count + 1; end if ; end process ; q<= (count); end Counter;  Cheers Don   --- Quote Start ---   Create a counter and use the MSB of the counter to drive the LED. The width of the counter is as many bits as is needed to blink at the rate you desire, eg., clock frequency x 0.5s for a half-second blink period.  Then when you get to the 7-segment display, you send the 4 MSBs of that counter (or one that is slightly wider) to a 4-input to 7-segment output decoder.  Take a shot at it, and then I'll show you some examples that use generics and floating-point math to calculate the bit-widths (the pre-processor does the math, rather than synthesizing it into hardware).  Cheers, Dave  --- Quote End ---  

[Altera_Forum]

Hi Dave 

 I had a shot at the 7 segment decoder and was quite pleased because I think I am almost there . It does count pulses, it does decode them, and it does display them correctly on a 7 segment display but,  it only does it if I use a switch to clock the circuit,  If I connect the count input to CLOCK_50 it turns on 6 of the seven segments and just sits there I thought at first it might be too fast but I dont think so as I am using the last 4 bits of a 27 stage counter   Here is the code I came up with  Library IEEE; Use IEEE.numeric_std.all; use IEEE.STD_Logic_1164.all; entity Led_Blink is port ( clk : in STD_Logic; q : buffer unsigned (27 downto 24); Dec_Out :out unsigned (6 downto 0) ); end Led_Blink; architecture Counter of Led_Blink is signal count : unsigned(27 downto 24); begin process (clk) begin if rising_edge (clk) then count <= count + 1; end if ; end process ; q<=(count); Process (q) begin case q is when "0000" => Dec_Out <= "1000000"; when "0001" => Dec_Out <= "1111001"; when "0010" => Dec_Out <= "0100100"; when "0011" => Dec_Out <= "0110000"; when "0100" => Dec_Out <= "0011001"; when "0101" => Dec_Out <= "0010010"; when "0110" => Dec_Out <= "0000011"; when "0111" => Dec_Out <= "1111000"; when "1000" => Dec_Out <= "0000000"; when "1001" => Dec_Out <= "0011000"; when others => Dec_Out <= "1111111"; end case; end process ; end Counter;   Don

[Altera_Forum]

Hi Don, 

 Excellent work.  Its much better for you to find things, try them, and then ask questions, and the questions are then meaningful to you.    --- Quote Start ---    I went online to find examples so I could see what they are doing and hopefully cobble some bits together to make mine  So far I had only used STD_LOGIC_1164 but looking online the example that looked most usefull used IEEE.Numeric.STD From this I think they used " Unsigned " .  To be honest I dont understand why they used it but gave it a go anyway    --- Quote End ---    VHDL is a type-safe language. It will not let you do something without first seeing a function that says a particular function is safe. For example, std_logic_vector just defines a vector of bits, whereas signed and unsigned define vectors of bits with mathematical operations, eg., you can add and subtract to signed and unsigned numbers, since they are supposed to be interpreted as numbers, not just bits on a bus or in a regsiter.    --- Quote Start ---    I made my entity with a clk input and q output (27 downto 0) for the architecture I declared a signal called count and told it  on the rising edge of clk to assign the value of " count + 1 " to the present value of "count" then told it that "q" is assigned this new updated value of "count"  It took a few goes to get the syntax right so that everything compiled ok  but eventually got there   --- Quote End ---    Great!    --- Quote Start ---    I assigned the pins so that the 50Mhz clk went to the clk input and I chose several tries at which "q" I used for the output till I found that q(24) seemed a good speed    --- Quote End ---    log2(50M) = 25.6-bits, i.e., a toggle rate of about 1 second will occur for a 26-bit counter, so your LED would have appeared to blink once every second or so.    --- Quote Start ---    I programed it to the DE2-115 and it did exactly as I wanted , flashing the first LED on and off , but for some reason there are random characters running across the LCD screen too, I dont know why as I have assigned no other pins ?   --- Quote End ---    If you checked the .pin file and the LCD pins were defined as INPUT or INPUT_WITH_WEAK_PULLUP or something like that (maybe it is RESERVED, I forget, its been a while since I've looked at a .pin file), then those characters could just be left over from the default design that loads at power-on.    --- Quote Start ---    Once this was working I made a second copy of the program but this time assigned the outputs Q24-Q27 to four LEDs and instead of feeding pulses from the  50Mhz clock I used one of the push buttons , so that it gave a binary count on the LEDs that increased with each push of the button  It skipped now and again but I expect that is just switch bounce   --- Quote End ---    That sounds about right. Although if you connected the LEDs to the MSBs of your counter, you would have had to press the switch about 50 million times to see them blink ...    --- Quote Start ---    I have been thinking about the 7 segment display and decoding it  I can see that if I take my 4 bit binary output from this last design that I could possibly work out how to decode it using case statements. If I make it have (3 downto 0) for the 4 inputs and (6 downto 0) for the 7 outputs to the segments  What I am not sure of is can I make this second entity and architecture for the decoder in the same file as the counter section or can I only have one entity per VHD file  in which case I am not sure how I make one file talk to the other , thats something else I must read up on   --- Quote End ---    You've described the right circuit. You can start to cheat now. I've posted a DE2 example to the forum in the past (different board than you have);  See Post#5 http://www.alteraforum.com/forum/showthread.php?t=33462  See Post#2 http://www.alteraforum.com/forum/showthread.php?t=35687  See Post#9 http://www.alteraforum.com/forum/showthread.php?t=45770  This last one includes a Modelsim simulation. You'll want to learn how to use the simulator.  If you take a look at my examples that blink an LED, you'll see them parameterized using generics. This is so that you can change the generics in simulation. For example, there is no point in waiting 1 second for an LED to blink in simulation, as that takes way too long to run. Using generics allows you to change the functionality of the design without changing the code (since the generics can be changed on the "command-line" of the synthesis or simulation tool).  Cheers, Dave

[Altera_Forum]

Your code is not quite right ... your counter is not 28-bits wide. You've solved a synthesis error by reducing your counter width. Here's the fixed code; 

Library IEEE; Use IEEE.numeric_std.all; use IEEE.STD_Logic_1164.all; entity Led_Blink is port ( clk : in STD_Logic; q : out unsigned (3 downto 0); Dec_Out :out unsigned (6 downto 0) ); end Led_Blink; architecture Counter of Led_Blink is signal count : unsigned(27 downto 0); signal q_out : std_logic(3 downto 0); begin -- 28-bit counter process (clk) begin if rising_edge (clk) then count <= count + 1; end if ; end process; -- Extract the 4-MSBs and cast unsigned to std_logic_vector q_out <= std_logic_vector(count(27 downto 24)); -- 4-bit output (pre-VHDL-2008 would not let you read 'output' ports) q <= q_out; -- Decode the 4-bit count Process (q_out) begin case q_out is when "0000" => Dec_Out <= "1000000"; when "0001" => Dec_Out <= "1111001"; when "0010" => Dec_Out <= "0100100"; when "0011" => Dec_Out <= "0110000"; when "0100" => Dec_Out <= "0011001"; when "0101" => Dec_Out <= "0010010"; when "0110" => Dec_Out <= "0000011"; when "0111" => Dec_Out <= "1111000"; when "1000" => Dec_Out <= "0000000"; when "1001" => Dec_Out <= "0011000"; when others => Dec_Out <= "1111111"; end case; end process ; end Counter;   Note how I created an internal signal q_out with the 4 MSBs of the counter that was then used as the input to the 7-segment decoder logic? If I did not do that, I would have had to define the q output as buffer. That does not descibe the logic "correctly" as far as I am concerned, so I typically introduce an internal signal. I'm pretty sure VHDL-2008 allows you to read "output" ports, but I don't mind the coding style of using internal signals, so I still use them.  Cheers, Dave

[Altera_Forum]

Hi Dave 

 Thanks for the last 2 replies and the encouragement I looked at what you had changed in my code and I think its making sense to me , however I tried compiling it and it failed   Part of your code said  architecture Counter of Led_Blink is signal count : unsigned(27 downto 0); signal q_out : std_logic(3 downto 0); **** This is the line the compiler comlains about   however Quartus claims , Error (10380): VHDL error at Led_Blink.vhd(21): std_logic type is used but not declared as an array type  and I dont know enough to know why its telling me this   In your first post you sent 3 links to code you posted previously that I couild look at and get ideas from . I have had a very quick look but I think its beyond my capabilities at the momment , its talking about starting the TCL console and I havent looked at TCL yet but , I will have a proper look and see what I can make of it , but it may be for further along my learning curve  Don

[Altera_Forum]

--- Quote Start ---   I tried compiling it and it failed    --- Quote End ---   Sorry, that is what I get for typing it into the forum directly - it should be std_logic_vector.    --- Quote Start ---   In your first post you sent 3 links to code you posted previously that I couild look at and get ideas from . I have had a very quick look but I think its beyond my capabilities at the momment , its talking about starting the TCL console and I havent looked at TCL yet but , I will have a proper look and see what I can make of it , but it may be for further along my learning curve   --- Quote End ---   Unzip the zip files and look at the VHDL. You can blindly follow the procedure to synthesize or simulate the design, and that will show you you have some working code.  Cheers, Dave