Another beginners question

[Altera_Forum]

Being new to FPGA's ( started yesterday ) when I was given an Altera DE2-115  

I find I keep coming up with lots of questions that I dont know the answer to  I have been reading all I can in the way of tutorials etc and I tried entering a simple example that I found online  to make a 2 way switch ( basically a 2 input exclusive or gate)  I built it first in the schematic design method as it sounded easier and it worked fine  I then built it using VHDL and that also works great but that raised my first question which is....  if I build it using Schematic design , will Quartus let me convert it into a VHDL file that I can look at to see how it would be written that way and vice versa if I write it using VHDL can Quartus convert it into a schematic design that I can view to see if its what I intended ?  and if that is possible how do I do it ?  I have lots of other questions but I wont be greedy so I will ask just one more for now   Being new to FPGA's I have installed the latest free edition of Quartus II which is V15.0.0 64 bit  I had down loaded a tutorial called " my first NIOS II for Altera DE2-115 but when I tried to follow it  it told me to open Tools/SOPC Builder which my version of Qaurtus doesnt have . I looked online for answers and it seems SOPC Builder no longer appears in the newer versions of Quartus and to use QSys instead  so does any one know if there is an equivelent to "My First Nios II " as a tutorial but written for Qsys rather than SOPC  Regards Don

[Altera_Forum]

Hi Dave  

Altered the faulty line to change q_out from std_logic to std_logic_vector and still compiling failed but this time I was able to sort it out myself   the output of my counter " q " takes the value of your " q_out" in the line q<= q_out; but near the begining where " q " is declared in the counter entity It had it as an unsigned , I changed it now to also be a std_logic_vector and it works fine now  I even added a bit more decoding to use all the counts of the 4 bits and I now get 0-9 and A-F  I left the lines in ...  when others =>  Dec_Out <= "1111111"; If I understand it correctly thats so it wont try to display something if one of the outputs were to become an undefined or high impedance type output  Out of interest I know I use <= to assign the value of the item on the right to the one on the left as in the line q <= q_out but in the case statement there are a lot of => symbols , what does => signify ? like  when others =>  Dec_Out <= "1111111";  I will look at the 3 links you gave me in the morning when I am more awake ( its been a long day) and taking of that  I had told my wife that judging from your user name , you are at Caltech, She said as you have already answered my last mail you must be up quite early, Are you not about 8 hours behind us ?  Don

[Altera_Forum]

--- Quote Start ---  Hi Dave  Thanks for the last 2 replies and the encouragement I looked at what you had changed in my code and I think its making sense to me , however I tried compiling it and it failed   Part of your code said  architecture Counter of Led_Blink is signal count : unsigned(27 downto 0); signal q_out : std_logic(3 downto 0); **** This is the line the compiler comlains about   however Quartus claims , Error (10380): VHDL error at Led_Blink.vhd(21): std_logic type is used but not declared as an array type  and I dont know enough to know why its telling me this  --- Quote End ---    It's a typo -- the signal q_out should be declared as a std_logic_vector(3 downto 0);

[Altera_Forum]

Hi Don, 

 The difference between <= and => is really just "syntax". For example, it gets used to separate the case-statement entries from their conditions. It could have just has easily been :.  Another place you will see it used is in assignments, eg., to initialize a std_logic_vector to all zeros you can use ...  signal q_out : std_logic_vector(3 downto 0) := (others => '0');    --- Quote Start ---   I had told my wife that judging from your user name, you are at Caltech, She said as you have already answered my last mail you must be up quite early, Are you not about 8 hours behind us ?   --- Quote End ---   Yeah, I'm in Pasadena, CA. I check the forum when I get up (7am or so) and then again later in the evening (after 9pm).  That gives you long enough to think about the problem/errors you encounter, and take a shot at solving them yourself :)  Cheers, Dave