Architecture generation question

[Altera_Forum]

Hi, 

 I have some questions about such an architecture:  https://www.alteraforum.com/forum/attachment.php?attachmentid=9219   As you see, I have two paths in my pipeline, but they are not conditional. Both have to be executed at all times.  If I write each path one after the other, like the following, is the compiler intelligent enough to detect there are no memory dependencies and make the arrangement shown previously?   out = in*2; out = in+4;   Or does it generate something like the following in my pipeline, where the y axis represents the pipeline stages?  https://www.alteraforum.com/forum/attachment.php?attachmentid=9220   Or... performance wise, do I have to actually care? Here the problem is simple enough, but in my real kernel, each branch is very big, with inner loops and lots of stuff.  Regards,  Smith

[Altera_Forum]

Yes, the compiler will load, then perform the multiplication and addition in parallel, and because you are storing to sequential locations coalesce that into a single store operation.

[Altera_Forum]

Suppose the store location depends on a random number, so that they cannot be coalesced, and that the number of instructions in each branch is different.. Are they still going to be executed in parallel?

[Altera_Forum]

In that case I believe it will look like a combination of the two diagrams where you'll have to store sites but each executing in parallel. If possible you should try to avoid random accesses like that since they are not ideal for SDRAMs.

[Altera_Forum]

Okay, thanks!