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15481 Discussions

Are VHDL source code templates available in ModelSim IntelFPGA?

JCosp
Beginner
1,098 Views

I have noticed that the option exists in standard ModelSim versions but I have not found it in IntelFPGA versions.

0 Kudos
5 Replies
MuhammadAr_U_Intel
169 Views

Hi,

 

May I know what version of Modelsim you are referring to where VHDL code templates are available ?

 

Per my knowledge there are some sample code available in Modelsim SE/ Modelsim Intel Edition stored in installation directory.

<installation directory>\modelsim_ase\examples\tutorials\vhdl

 

Thanks,

Arslan

Vicky1
Employee
169 Views

Hi,

I could not understand your question, Can you please tell, where did you find that option in standard ModelSim versions.

 

Do you mean template available under "file -> New -> Source -> VHDL" in ModelSim Intel FPGA?

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

JCosp
Beginner
169 Views

Hi,

 

I am using version 18.0 (IntelFPGA) which corresponds to version 10.5b from Mentor.

I have checked the user's manual and I realized that in older versions (10.1) it says that you can open language templates by selecting 'Source→Show Language Templates' when the source window is open (User's Guide 10.1b page 465). However, I have not found an equivalent statement in the User's Guide for version 10.5b.

Could have this option been removed in newer versions?

 

Best Regards,

MuhammadAr_U_Intel
169 Views

Hi,

 

Yes I checked user manual for older version Source Window language template is removed starting Modelsim Version 10.3

Modelsim User's manual page 47, "Table 1-8. Deprecated Features"

 

Alternatively you can make use of Verilog/ VHDL language templates provided with Quartus Prime.

Refer to user guide below on how to access them.

https://www.intel.com/content/www/us/en/programmable/documentation/sbc1513987577203.html#mwh14099595...

Topic: Using Provided HDL Templates

 

 

Thanks,

Arslan

bitwise
New Contributor I
169 Views

​There are still templates for VHDL/Verilog/SystemVerilog built into QuartusII. 

 

To use them, open a text editor window ("File/New" then select your HDL of choice) then either

(a)  Right-click in the text window and select "Insert Template",

(b)  Select "Edit / Insert Template" from the QuartusII menu, or

(c)  Left-click on the scroll icon that is in the text editor toolbar.

 

These templates are for synthesis.  If you want a test bench template then open your compiled project in QuartusII and select "Processing / Start / Start Test Bench Template Writer".

 

Hope that helps.

 

Craig

 

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