Array data type conflicts with std_logic_vector definition.

[CBart19]

I would like to use a arrays of standard logic vectors of two different lengths so I declare two new data types.

 type tx_vector is array (0 to 14) of std_logic_vector(17 downto 0);

 type rx_vector is array (0 to 14) of std_logic_vector(24 downto 0);

I then declare a signal using the tx_vector data type:

signal slave_com_tx_data : tx_vector;

But apparently this definition messes up the std_logic_vector definition? Later on in the code I have this line:

Iq_ref      <= signed(std_logic_vector("000"    & A_temp(7 downto 0)));

Where "A_temp" is declared as a simple std_logic_vector. The compiler throws these errors:

Error (10327): VHDL error at FCMLctrl.vhdl(868): can't determine definition of operator ""&"" -- found 5 possible definitions

Error (10647): VHDL type inferencing error at FCMLctrl.vhdl(868): type of expression is ambiguous - "rx_vector" or "tx_vector" are two possible matches

Error (10411): VHDL Type Conversion error at FCMLctrl.vhdl(868): can't determine type of object or expression near text or symbol "std_logic_vector"

Why does my declaration change the way simple std_logic_vectors operate?

I am using these libraries

 library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;

 use IEEE.NUMERIC_STD.ALL;

Thank you for any assistance you may be able to provide.

[CBart19]

It seems things work if I construct the arrays in two steps from std_logic elements.

   type tx_vector is array (17 downto 0) of std_logic;

   type rx_vector is array (25 downto 0) of std_logic;

   type tx_array is array (natural range <>) of tx_vector;

   type rx_array is array (natural range <>) of rx_vector;

I can then use the tx_array and rx_array.

Is there a reason for this?

This is not what I need. Ultimately, I need an array of std_logic_vectors.

[Kenny_Tan]

Which version of Quartus that you were using? Pro or std? Can you put your design.qar here so that I can look into the error?

[RRomano001]

Hi CBart, just curios about:

Iq_Ref how and where is declared?

Rx Tx are different from.

What at lines 868 and few lines before 868 can fire there error.

Aggregate has 11 bit is Iq_ref a signed vector 11 bit long or in range?

If A_temp is an Std_logic vector why typecast aggregate of same type?

VHDL is strongly typed and rigid, also deterministic so I like that also if something require a lot of coding.

Try if this help clarify

http://www.bitweenie.com/listings/vhdl-type-conversion/

Regards

Roberto

[Kenny_Tan]

Hi Chris, Is there any update?