Array implementation in VHDL and calculating the average of elements in the array

Altera_Forum · ‎11-17-2012

I have a Home assignment to be done in VHDL to find out the average of the elements of an array and then subtract thrice the average from each of the array elements. Then the elements greater than zero must be made zero..I've written the following code in Xilinx ISE..I'm new to VHDL

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 22:52:57 10/30/2012

-- Design Name:

-- Module Name: rem_trend - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rem_trend is

end rem_trend;

architecture Behavioral of rem_trend is

type rem_trend is array(15 downto 0) of real;

sum = 0;

for j in 0 to length[rem_trend] loop

sum = sum+rem_trend[j];

end loop

sum = sum/length[rem_trend];

for i is 1 to 3 loop

for j is 0 to length[rem_trend] loop

rem_trend[j] = rem_trend[j]-sum;

end loop

for j is 0 to length[rem_trend] loop

if (rem_trend[j]>'0') then

rem_trend[j] = 0;

end if;

begin

end Behavioral;

-----------------------------------------------------------------------------

Any help in this regard will be worth a million thanks...I don't know why this doesn't work and what exactly I need to add?

Altera_Forum · ‎11-18-2012

--- Quote Start ---

I don't know why this doesn't work and what exactly I need to add?

--- Quote End ---

Missing are

- definition of signals and variables

- declaration of port signals connecting in- and outputs

Necessary corrections (at least)

- correct VHDL assignment syntax

- correct VHDL array index syntax

- use a legal VHDL attribute instad of length[xxx]

- use synthesizable types instead of real

As you apparently missed your VHDL lectures, you should consider a good text book.

Altera_Forum · ‎11-18-2012

Thank you, Could you refer me a good text book wherein I can learn VHDL

Altera_Forum · ‎11-19-2012

"VHDL : Programming By Example" by Douglass Perry <- Great choice for beginners.

Altera_Forum · ‎11-26-2012

I tried this code after going through that book....

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 18:44:30 11/26/2012

-- Design Name:

-- Module Name: average - rem_trend

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

package but is

type mat_arr is array(0 to 31) of std_logic;

type rem_tre is array(0 to 31) of std_logic;

end but;

use work.but.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity average is

port (

data : in mat_arr;

a : in integer;

data_out : out rem_tre);

end average;

architecture rem_trend of average is

begin

process(data, a)

begin

for i in 1 to 31 loop

line-50 data(i) <= data(i-1) + data(i);

end loop;

end process;

end rem_trend;

But while running in Xilinx ISE 14 I get the following error: ERROR:HDLParsers:808 - "C:/Users/vicky/array/average.vhd" Line 50. + can not have such operands in this context.

I require a quick reply. Meanwhile I'll be trying... I would be very thankful for any help

Altera_Forum · ‎11-26-2012

You cannot add together a std_logic and a std_logic. I also suggest you never make a custom array of std_logics either. Thats what std_logic_vector is for. If you make you're own, then none of the functions that work with std_logic_vector will work with your type.

Altera_Forum · ‎11-27-2012

DO you mean to say that I need to declare a std_logic vector rather than an array ?? Could you explain why? Also I will get an array as an input from the computer. So how to store the elements in vector?

Altera_Forum · ‎11-27-2012

I would recommend using std_logic_vector. A std_logic_vector is just an array of std_logic:

signal my_slv : std_logic_vector(31 downto 0);

Altera_Forum · ‎11-27-2012

I understand that the intended application purpose is adding multiple numbers. If so, a suitable mat_arr type would be array of signed, unsigned or std_logic_vector. Personally, I prefer explicite numeric types.

Altera_Forum · ‎11-27-2012

I tried this code

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 18:44:30 11/26/2012

-- Design Name:

-- Module Name: average - rem_trend

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use ieee.numeric_std.all;

package but is

type mat_arr is array(0 to 31) of real;

end but;

use work.but.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity average is

port (

data : in mat_arr;

data1 : in mat_arr;

data_out : out mat_arr);

end average;

architecture rem_trend of average is

signal my_int : mat_arr;

begin

process(data,data1,my_int)

variable a1 : real;

variable b : real;

begin

for i in 0 to 31 loop

my_int(i)<=data(i);

end loop;

a1:=0.0;

for i in 0 to 31 loop

line 59 a1:=a1+my_int(i);

end loop;

b := a1/32.0;

for i in 0 to 31 loop

my_int(i) <= my_int(i)-(3.0*b);

if (my_int(i) > 0.0) then

my_int(i) <= 0.0;

end if;

end loop;

for i in 0 to 31 loop

data_out(i)<=my_int(i);

end loop;

end process;

end rem_trend;

but it shows error at line 59... real operand is not supported in this context!!!!

please help...tomorrow is the last day for submission

Altera_Forum · ‎12-04-2012

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 18:44:30 11/26/2012

-- Design Name:

-- Module Name: average - rem_trend

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity average is

port (

b : in std_logic_vector(31 downto 0);

data_out : out std_logic_vector(31 downto 0));

end average;

architecture rem_trend of average is

begin

process(b)

variable a1 : integer;

variable c1 : real;

begin

for i in 1 to 31 loop

b(i) := b(i-1) + b(i);

end loop;

a1 := b(31);

c1 := a1/32;

for i in 0 to 31 loop

b(i) := b(i)-(3*c1);

if (b(i) > 0) then

b(i) := 0;

end if;

end loop;

for i in 0 to 31 loop

data_out(i)<=b(i);

end loop;

end process;

end rem_trend;

I tried this code.. removed package and put std_logic_vector..it gives me 2 errors HDL parsers 800 and HDL parsers 808

Altera_Forum · ‎12-04-2012

b(i) is a std_logic, you cannot compare it to any number, because it is not a number, just a single bit.

Altera_Forum · ‎12-04-2012

I got the errors.. changed them a little bit.... Now it implements the design but during the mapping it gives 2 errors : too many "slicel" being used...(overmapped)

Altera_Forum · ‎12-05-2012

Error messages specific to Xilinx tools should be discussed in a Xilinx forum.

Generally speaking, I'n not under the impression that your code will be synthesizable in an actual FPGA.