Array of an element

[Altera_Forum]

Sorry if this is a basic question but how do I specify an array of elements in the schematic? 

 I have a shift register element and need 16 of these. So I made a symbol for the element and tried setting its instance name as Shift[15..0] then attaching busses or signals to its pins.    What I am assuming is that a 16 bit bus attached to a bus will be on a per bit basis, attaching a signal to a bus connects all bus elements to that net name.   This doesnt seem to work, what am I doing wrong? Point me at an example if there is one.

[Altera_Forum]

You forgot to attach the files but arrays are done with subscripts. For example if I wanted a 16 bit bus I could label the bus line "my_bus[15..0]". If you connect a 16-bit output to a 16-bit input of another block using a bus line there is no need to label the bus line.  

 Typically you label the bus lines when you want to do bit manipulations. For example if you have a 16-bit register that you want to wire up to pins you can create a bus line and connect it to nothing but label it "my_bus[15..0]". Then you can draw individual wires to pins labelled my_bus_out[0], my_bus_out[1], .... my_bus_out[15]. I have attached an example of this (note if you were wiring the entire bus to pins I would just use a single pin called "my_bus_out[15..0]" and wire it up directly).

[Altera_Forum]

So in your example, you attach a 16 bit bus to a single DFF element. Does the act of doing that create an array of 16 DFF's?  

 I guess I was expecting to need to tell Quartus that 16 DFF's are needed somehow.

[Altera_Forum]

Yep that's correct, the flipflop will become 16 bits wide in that case. In that schematic I didn't use the megawizard to parameterize the flipflop, I just selected it directly and added it so Quartus uses information about what's hooked up to it to figure out how it should be parameterized. If you incorrectly labelled the input and output of that register with different widths then you should get an error or warning depending on which one is wider (I haven't done schematic design in many years so just going by memory). 

 You probably noticed those wires/buses that are labelled but don't go anywhere. Quartus uses name matching to join nets with the labels that have the same names. If you have used other schematic tools for board design this is typically called an 'alias' and the same rules apply. When I was doing a lot of schematic entry I would use them to keep my schematic clean, otherwise you'll have wires and buses wrapping around blocks which makes it hard to follow sometimes (imagine having 30 clock connections and the mess that would make if you didn't use aliases :))

[Altera_Forum]

This works great unless I make a new block. If I wire the symbol up to a bus, I get compilation errors. It's like a library element has some sort of property that allows the bus connection/expansion, but a user generated symbol does not behave the same way??

[Altera_Forum]

That's correct, for custom IP you'll have to set the width accordingly before connecting the bus. I'm not sure if there is a way to make a custom IP core parameterizable at a schematic level... by the time I started needing that sort of thing I gave up on schematics and switched to VHDL/verilog.