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Arria 10 Native Floating Point Adder Issue

corestar
New Contributor I
231 Views

I'm using Quartus 19.1 Standard and there is an odd issue with the native Arria 10 floating point adder. As shown in the attached, the Ax input has a latency of 3 clocks but the Ay of only two. So the output is not Ax + Ay at the same clock cycle. If I add an external register stage to Ay, it works as expected.  The extra register in Ax does not seem to server any purpose and seems like an odd design choice.

Am I missing something?

The native multiplier works as expected with a latency of 3 clock cycles. 

 

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1 Solution
SengKok_L_Intel
Moderator
221 Views

Hi,


You can actually click on that register from the Native DSP Block floating Point GUI to change the clock source and also disable that register if this is not required.



Regards -SK


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3 Replies
SengKok_L_Intel
Moderator
222 Views

Hi,


You can actually click on that register from the Native DSP Block floating Point GUI to change the clock source and also disable that register if this is not required.



Regards -SK


View solution in original post

corestar
New Contributor I
210 Views

@SengKok_L_Intel ,

That worked! Thanks so much for the help.  And I can reduce the multiplier latency, at the expense of Fmax, in the same way.

I'd suggest that removing that register might be a sensible default for an adder.

 

 

SengKok_L_Intel
Moderator
194 Views

Thank you for the feedback.


If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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