Dear all,recently I got an Arria 10 FPGA board on which I want to use the OpenCL toolkit. According to the DE5ANET_I2 board OpenCL manual, the board should be flashed with hello_world.aocx OpenCL image via command: aocl flash aclde5a_net0 hello_world.aocx and then I got error like the following: ================================================================================================================== Info (209005): Programming status: programming flash memory at byte address 0x0FFF0000 Error (209053): Unexpected error in JTAG server -- error code 12 Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Wed Jan 25 16:52:17 2017 Error: Quartus Prime Programmer was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 3300 megabytes Error: Processing ended: Wed Jan 25 16:52:17 2017 Error: Elapsed time: 00:02:17 Error: Total CPU time (on all processors): 00:00:44 Error: quartus_pgm failed at /root/altera_pro/16.0/hld/board/de5a_net_i2/linux64/libexec/flash.pl line 74, <STDIN> line 1. aocl flash: Program failed. ================================================================================================================== Has anyone met this issue? Hope you can help. Schieben
Yeah, aocl diagnose cannot give proper results before executing aocl flash. I've used root, tried killall -9 jtagd and jtagconfig gives results seems right:# jtagconfig 1) DE5 [2-1.4] 02E060DD 10AT115S(1|2) but still the same error.
--- Quote Start --- Try jtagconfig -c 1 --setparam <cable name> JtagClock 6M In my case using the USB-Blaster I use jtagconfig -c 1 --setparam 1 JtagClock 6M --- Quote End --- So what should the value of <cable name> be, is it 2 if I use the USB-Blaster II?
--- Quote Start --- Try jtagconfig -c 1 --setparam <cable name> JtagClock 6M In my case using the USB-Blaster I use jtagconfig -c 1 --setparam 1 JtagClock 6M --- Quote End --- Well, succeeded after executing this command, thanks very much! But could you tell me what is the reason?
The answer I got to the same question from an Altera engineer was"About the jtag clock programming, 24M is the standard speed but, for our system, it needs to be set at a lower frequency (i.e. 6). "
Was that an engineer from Altera or from the board manufacturer? It is highly unlikely that this problem is related to Altera; it seems to be due to defect or bad design of the JTAG controller by the board manufacturers. I have tried two different Arria 10 boards from two different manufacturers and one of them works just fine with 24M clock, while the other one only works with 16M and lower, and in the latter case, the manufacturer also mentions the problem in their user guide. Needless to say, 6M is too low and will significantly increase programming time on Arria 10. I recommend first trying with 16M (which is quite slow as it is) and if it didn't work, going down to 6M.