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Arria5 GX Transceiver Clocking Question, using internal clock on more than 4 transceivers?

ThomasTessier
New Contributor I
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Support,

 

I have a design which is working with 4 transceivers and each transceiver is treated independently from the standpoint of our HDL design. The transceivers are driven on the pins: rx_cdr_refclk and tx_pll_refclk from a AlteraPLL.  We are really using the transceivers as PHY only -- this is a completely custom protocol.

I have the need to expand from 4 transceivers to 6 transceivers. I felt I could just expand the number of "by1" transceivers from 4 to 6. But alas QuartusPrim 21.x has other ideas.  I believe this is due to the clocks are shared by a group of 4 transceivers but are not shared by all the transceivers on the same side.  Yes I am trying to use 6 transceivers on the same side of the die.

In reading through the manual it seem I am attempting to use xN Native Phy clock network. I have read the description but don't understand how to directly implement what is said.  What I would like to implement is my one PLL drives all transceivers on a side!

Do I need a second PLL running from the same clock source which generates the same frequencies and attach that to the 2 new transceivers?  How do I manage the phase difference of these two transceivers with respect to my RTL which is interfacing via one of the clocks?

I am leveraging an Arria5 development platform and I must use internal clocking because of some external interfaces which are already set up.  So I have a lot of limitations on choice of clocks and such -- a limitation that maybe we could overcome but not without much delay and lots of "why" meetings.

Looking for guidance as I believe this comes down to clock management of the transceivers in the Arria5 GX part.  It just isn't clear if you are using this in Native PHY mode.

TomT...

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Kshitij_Intel
Employee
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Hi,


Can you please share the below details.


  1. Which Operating system you are using?
  2. Which Quartus Software version you are using?
  3. Which device(OPN) you are targeting?


Thank you

Kshitij Goel



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ThomasTessier
New Contributor I
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Device: 5AGXFB3H4F35C4

OS: Linux CentOS 7

Tool Version: QuartusPrime 21.1.0.842

 

This is a development card so the only transceiver pins I can use are as follows:

G3, J3, L3, N3, R3, U3, W3, AA3 -- TX_P

H1, K1, M1, P1, T1, V1, Y1, AB1 -- RX_B

 

The clock is internally generated, yes I know the Jitter will be higher but that is what I have available.  This design uses a home grown protocol so we just need the Transceivers for SERDES operation, we are bypassing much of the logic. I have this working with 4 transceivers but now need to expand to 6 transceivers.  That is where the issue resides.

Thanks,

TomT...

 

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Kshitij_Intel
Employee
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Hi,


Please specify the data rate, that those transceivers need to run at, as this will also determine what you can use. Unfortunately AVGX doesn't support fb_compensation clocking like in SVGX or AVGZ which is ideal to have always the same phase at startup w.r.t. the reference clock (this is you want I believe). So to have the next best option you would have to use x6 clocking (x6_fPLL) but data rate limited to 3.125 Gbps or xN clocking using CMU PLL (requires 7 channels to clock 6 transmitters) which according to the datasheet is limited to 5 Gbps (but not restricted in Quartus apparently). I suggest you refer to this document which gives all options https://cdrdv2.intel.com/v1/dl/getContent/683573


Thank you

Kshitij Goel


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ThomasTessier
New Contributor I
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The serial data rate is 2.912Gbps, well within the specification for the device.

So it sounds like I need a different configuration for my Transceivers than I have now to use the x6_fpll which would support attaching up to 8 transceivers from the same internally generated PLL?

I would say there are answers in that manual but they are not organized in a way to answer if you want to use the Transceivers in a not standard way which is what I am trying to do.  The questions are hard and the answers are even harder to find.

If I was building something that was using PMA Direct at that data-rate and wanted to use an internally generated 182MHz source clock (x16 to get to 2.912GHz) and connect up to 8 transceivers can I do it with the Pins I mentioned above?

Thanks,

TomT...

 

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Kshitij_Intel
Employee
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Hi,


As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you

Kshitij Goel


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