Assign SDC files on each VHDL component project

[Altera_Forum]

Hi everyone, 

 I need help here.  I have a FPGA VHDL project, the project consist of several independent component (also made in VHDL) which are arranged into a single large project (top level entity). The project is created in a structural folder, so each project can be edited independently. Now, project entering Timing Analysis stage using TimeQuest Timing Analyzer which I'm not really familiar with TimeQuest, SDC, etc. Currently I learning those things right now.   I'm planning to constraint each component first and include sdc file into top level project as if it is a VHDL component, but it seem it didn't work in that way. I realize that this is my mistake, such as INPUT PORT in a component can be correctly constrained as PORT(SDC) in constraining component project, but not in top level entity, because it will not recognize as INPUT PORT, maybe recognized as node, keeper, gate or something else.  That is problem for me.  Does anyone here has knowledge related to my problem, so timing constraining of each component will be possible? I would like to constraint each component first, because I think it will divide project scope into smaller scope so it can be easy to debug later. Other solution is also welcome.  Thanks, Any kind of help will be appreciated. :) Please help me,... :)

[Altera_Forum]

You should only constrain the FPGA's pins in the SDC file, all the internal signals timings between two VHDL components are automatically handled by Timequest. 

The only component specific timing constrains you way need to add at a component level are multicycles and false paths.

[Altera_Forum]

I think it is better to constrain only the top level entity. 

This allows Timequest to automatically optimize the internal components.

[Altera_Forum]

I think what rochmadp is asking is: is there a way to automatically incorporate .sdc files from a lower level in the top level? 

Some of the module ones designs have to do with specific hardware and is often re-used in other projects. E.g. a high-speed LVDS parallel bus input (as from ADCs, CMOS sensors, ...) is a low level module which you ideally design at its smallest, just the physical pins and some internal ports. To see whether the module will fly you actually have to constrain the inputs, hence you write a small .sdc file. But later on when you include the lower level module in the top design one has to manually (a lot of copy/paste) re-create the SDC constraints. Of-course the Altera Gurus do this all with Tcl-scripts (and Perl, and ...).  An interim solution is to write the lowest level test module .sdc in 2 pieces. One that constrains the internal ports and a second, to be included by the first one, that constrains the physical pins. The higher level .sdc sets a few variables for the second one to use. This way the second .sdc is a bit easier to re-use in a top-level project as one only has to update the variable names.

[Altera_Forum]

Thank you everyone, 

 Daixiwen, nplttr, in my FPGA design data from main input is processed in one component, the result of processed data is passed again into next component using source synchronous data transfer, and it repeated again until four step before it passed to final output. Are you sure we only need to constraint only in top level entity?  Constraining false path and multicyles will be difficult(I think) especially in a design which each component operation depend on output of others components or main input. Internal component design operation is not based on the time, but input (in this case, I connect it to a controller which will send instruction to my design, and It will send instruction as It pleased).  Jobsyb,   --- Quote Start ---   I think what rochmadp is asking is: is there a way to automatically incorporate .sdc files from a lower level in the top level?   --- Quote End ---     yes, that is what I mean, so basically we can't incorporate original lower level sdc files? We need to recreate it based on original sdc files for top level entity? Is there any automatically way to do it? or it already included in altera software or timequest sofware?  Thank you, and sorry for many question :), I'm still learning on this things,...

[Altera_Forum]

As long as your source synchronous interface is inside the FPGA, and is described as such in your HDL code then there is no need to constrain it, it will be handled automatically by Quartus. You only need to constrain the input/output interfaces. 

False paths and multicycles shouldn't depend on the inputs, but on the way your components are internally designed. Usually false paths are necessary when you transfer signals from one clock domain to another, and multicycles if you have a long combinatorial block that you know will take several cycles to complete, and have designed your component in accordance. Those are specific cases, and if you don't think you need them, then you probably don't ;)