Assigning Capture Registers - How To?

[Altera_Forum]

I'm implementing a 300 MHz DDR interface to deserialise an octal LVDS ADC (in fact multiple of them). One of the messages fromQuartusII is: 

critical warning: fitter could not properly route signals from dq i/os to dq capture registers because the dq capture registers are not placed next to their corresponding dq i/os  info: dq capture register \genadc:2:adc|ddrin|auto_generated|input_cell_h[4] at (22, 1) is not assigned to the adjacent lab of the corresponding dq i/o adcserdata[2][4]~input at (23, 0) ... The corresponding Help message recommends the following action: action: ensure that the dq capture registers are assigned to labs adjacent to their corresponding dq i/os.  Can anyone serve me a document that tells me where these capture registers are hiding and how I can match them with the respective pins? I'm currently testing my project both in Cyclone II and Cyclone III.

[Altera_Forum]

If you search for the register name in the floorplan view, you can drag them around to place them. I would: 

 Search for ' \genadc:2:adc|ddrin|auto_generated|' in the chip planner Click the button to expand the nodes that drive those registers (which will be the pins) Now drag the pins to lock them down (if they are not placed already) And drag the registers to put them in the LAB directly above the pin. The lines joining the pin to the register should help.  You can also set the location with a command (from memory) set_instance_assignment -type location LAB_X23_Y1 \\genadc:2:adc|ddrin|auto_generated|input_cell_h\[4\]

[Altera_Forum]

Thanks for the reply, Cajun-Rat. 

 I just happened to be looking into the Floorplan editor and realised that this would help. But I never liked the Floorplan Editor because it never fits nicely on the screen. I'm convinced that Altera could easily document the pin to nearest LAB realtion or even better add a setting in the Assignment editor to automate binding/reserving a DDRIO pin to the nearest LAB register. If one wants DDRIO, one wants the full DDRIO allocated optimally not just half of it? I am evaluating multiple combinations : 4, 8 or 16 ADCs in either Cyclone II or Cyclone III devices, so you can appreciate that I'm a bit shy of the Floorplanner, and stick to the Pin Planner in order to optimize the layout of the PCB.