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Valued Contributor III
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Assigning XCVR_RECONFIG_GROUP constraint to transceiver's differential lane

Hi, 

 

 

I am testing Diaplay Port I/P on Altera's Arria 10 board. My top module has the following I/Os 

 

rx1_l0_p 

rx1_l1_p 

rx1_l2_p 

rx1_l3_p 

rx1_l0_n 

rx1_l1_n 

rx1_l2_n 

rx1_l3_n 

 

tx1_l0_p 

tx1_l1_p 

tx1_l2_p 

tx1_l3_p 

tx1_l0_n 

tx1_l1_n 

tx1_l2_n 

tx1_l3_n 

 

 

I need to make pin assignments to them and assign "HIGH SPEED DIFFERENTIAL I/O" constraints to them in QSF. 

Here, Quartus fitter takes compliment pin assignment automatically. That means, I have to assign PIN assignments to *_P pins only,  

if I assign "HIGH SPEED DIFFERENTIAL I/O" constraints to *_P pins. But doing so, it generates *_P(n) pins.  

 

 

But I don't want that. Please note that I can't change my top module or it's I/Os. 

 

 

So, instead of letting Quartus automatically assign compliment differential pin, can I assign the pins manually. Like this? 

set_location_assignment pin_aw7 -to rx1_l0_p 

set_location_assignment pin_aw8 -to rx1_l0_n 

set_instance_assignment -name io_standard "high speed differential i/o" -to rx1_l0_p 

set_instance_assignment -name io_standard "high speed differential i/o" -to rx1_l0_n 

 

 

 

 

Second question 

The above mentioned I/Os are transceiver channels. In Altera's reference design, they have following I/Os 

rx1_l0 

rx1_l1 

rx1_l2 

rx1_l3 

 

tx1_l0 

tx1_l1 

tx1_l2 

tx1_l3 

 

 

Here, they have drawn out only positive ends of differential I/Os 

And they have put each TX-RX channel pair under one XCVR_RECONFIG_GROUP 

 

 

set_instance_assignment -name xcvr_reconfig_group 1 -to tx1_l0 

set_instance_assignment -name xcvr_reconfig_group 1 -to rx1_l0 

set_instance_assignment -name xcvr_reconfig_group 2 -to tx1_l1 

set_instance_assignment -name xcvr_reconfig_group 2 -to rx1_l1 

set_instance_assignment -name xcvr_reconfig_group 3 -to tx1_l2 

set_instance_assignment -name xcvr_reconfig_group 3 -to rx1_l2 

set_instance_assignment -name xcvr_reconfig_group 4 -to tx1_l3 

set_instance_assignment -name xcvr_reconfig_group 4 -to rx1_l3 

 

 

 

 

In my top module, both (_P and _N) ends of differential I/Os have been drawn out 

RX1_L0_P 

RX1_L1_P 

RX1_L2_P 

RX1_L3_P 

RX1_L0_N 

RX1_L1_N 

RX1_L2_N 

RX1_L3_N 

 

 

TX1_L0_P 

TX1_L1_P 

TX1_L2_P 

TX1_L3_P 

TX1_L0_N 

TX1_L1_N 

TX1_L2_N 

TX1_L3_N 

 

 

What should I write in QSF to put TX-RX pair under same XCVR_RECONFIG_GROUP?
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Highlighted
Valued Contributor III
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Re: Assigning XCVR_RECONFIG_GROUP constraint to transceiver's differential lane

With Altera's tools you only code and constrain the positive half of differential signals. By virtue of the fact you're specifying the signals as a differential I/O standard Quartus will automatically assign the negative pin accordingly. 

 

So, no. You shouldn't be adding the constraints you listed. Code for "RX1_L0", for example. Then, in the constraints editor, by specifying this is a differential I/O standard it'll automatically create the assignment for negative pin when you specify the pin for the positive pin. 

 

I recommend you play around with the 'Pin Planner', with a simple project, exploring the I/O standards and see what .qsf entries result. I think that'll clear things up for you and help answer your second question too. Then you can write your .qsf file from scratch - if you wish. 

 

Cheers, 

Alex
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