Assigning individual bits

Altera_Forum · ‎02-05-2013

Hi all,

I'm a complete newbie in Verilog, so I have a question.

I have in my main Verilog file (irrelevant code stripped out):

//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================
module Lab2(
    //////////// SEG7 //////////
    HEX0,
    HEX1,
    HEX2,
    HEX3,
    HEX4,
    HEX5,
    HEX6,
    HEX7 
);
//////////// SEG7 //////////
output                     HEX0;
output                     HEX1;
output                     HEX2;
output                     HEX3;
output                     HEX4;
output                     HEX5;
output                     HEX6;
output                     HEX7;
    Default u0 (
        .id7seg_display_export        (???)
    );
endmodule

Now, Default.id7seg_display_export is declared as:

output wire id7seg_display_export // id7seg_display.export

My question is, how do I connect individual bits from id7seg_display_export to the different HEX outputs signals? I just can't figure it out because I don't know the syntax...

Altera_Forum · ‎02-06-2013

That's very simple. Some examples:

assign HEX0 = id7seg_display_export[6:0];

assign HEX1 = id7seg_display_export[13:7];

assign HEX2[0] = id7seg_display_export[3];

assign HEX2[4:1] = id7seg_display_export[12:9];

assign HEX2[6:5] = id7seg_display_export[20:19];

The last 3 above could even be companded into a single one:

assign HEX1[6:0] = { id7seg_display_export[20:19], id7seg_display_export[12:9], id7seg_display_export[3]};

Altera_Forum · ‎02-06-2013

Are you sure that works?

For doing

assign HEX2[0] = id7seg_display_export[3];

I get that id7seg_display_export is undefined. Slapping in uc, as in:

assign HEX2[0] = uc.id7seg_display_export[3];

gives another error, something like cannot resolve assign id7seg_display_export (dunno if this is right anyway).

BUT, I managed to get it working by using (yes, I changed the name):

.seg7_display_export ({HEX3, HEX2, HEX1, HEX0})

Altera_Forum · ‎02-06-2013

Sorry, You are right.

I didn't notice that id7seg_display_export is actually the name of the submodule port.

I treated it like a common signal

I mean, what I wrote should apply in this case, where the same name is defined for the top level signals

wire [27:0] id7seg_display_export;

Default u0 (

.id7seg_display_export(id7seg_display_export)

);

Altera_Forum · ‎02-06-2013

Oh, right, that's another way of doing it.

Thanks for the help!