Auto gated clock conversion

[Altera_Forum]

I've been referring to the handbook on auto gated clock conversion, but the explanation seems a bit confusing.  

   --- Quote Start ---   The gated clock conversion occurs when all these conditions are met: ■ Only one base clock drives a gated-clock ■ For one set of gating input values, the value output of the gated clock remains constant and does not change as the base clock changes ■ For one value of the base clock, changes in the gating inputs do not change the value output for the gated clock The option supports combinational gates in clock gating network.  This option does not support registers in RAM, DSP blocks, or I/O related WYSIWYG primitives. Because the gated-clock conversion cannot trace the base clock from the gated clock, the gated clock conversion does not support multiple design partitions from incremental compilation in which the gated clock and base clock are not in the same hierarchical partition. A gated clock tree, instead of every gated clock, is the basis of each conversion. Therefore, if you cannot convert a gated clock from a root gated clock of a multiple cascaded gated clock, the conversion of the entire gated clock tree fails.   --- Quote End ---    So the first bullet talks about only one set of base clocks can drive a gated clock. Then the last sentence has a jumble about cascaded gated clocks. Say I have a setup like this. CLKmain is my clock into the FPGA. CLKa and CLKb are both gated with an AND gate and a single control signal. CLKc is (gateCA & CLKa) | (gateCB & CLKb). I would imagine that CLKc can not be converted, but can CLKa or CLKb? If they can't why not? I would imagine you could add the control signals on the gate of CLKa and CLKb to the expression for CLKc and get something equivalent...  Thanks a lot,  Steve