Avalon BFM - Test Program

[Altera_Forum]

Hi, 

 I just succesfully generated my first Avalon BFM testbench with Qsys 14. I have a component that consist of my avalon entity and an additional library file that contains some system wide constants.  The Qsys "generate" procedure generated a big file structure with a testbenchfile that I suppose to use in some kind of "test program" that uses the BFM API described in the document "Introduction to Avalon Verification IP Suite".  I'm currently stuck where I have to set up a little tcl script that compiles my testbench design in modelsim. The script looks like this and is based on the BFM example found here: http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html (http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html)   # setup variables for simulation script set system_name ads1158_bfm_test_tb set QSYS_SIMDIR $system_name/simulation set TOP_LEVEL_NAME tb source $QSYS_SIMDIR/mentor/msim_setup.tcl # compile system dev_com com # compile testbench and test program # vcom test_program_pkg.vhd # vcom test_program.vhd # vcom tb.vhd # load and run simulation # elab_debug # do wave.do # run 50ns # alias to re-compile changes made to test program, load and run simulation # alias rerun { # vcom test_program_pkg.vhd # vcom test_program.vhd # elab_debug # do wave.do # run 50ns # }   If I call this in modelsim, the output is as follows:  do run_ads_1158_bfm_simulation.tcl # ads1158_bfm_test_tb # ads1158_bfm_test_tb/simulation # tb # file_copy # List Of Command Line Aliases # # file_copy -- Copy ROM/RAM files to simulation directory # # dev_com -- Compile device library files # # com -- Compile the design files in correct order # # elab -- Elaborate top level design # # elab_debug -- Elaborate the top level design with novopt option # # ld -- Compile all the design files and elaborate the top level design # # ld_debug -- Compile all the design files and elaborate the top level design with -novopt # # # # List Of Variables # # TOP_LEVEL_NAME -- Top level module name. # # SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module. # # QSYS_SIMDIR -- Qsys base simulation directory. # # QUARTUS_INSTALL_DIR -- Quartus installation directory. # dev_com # com # Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013 # # Top level modules: # --none-- # Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013 # # Top level modules: # --none-- # Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013 # # Top level modules: # --none-- # Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013 # # Top level modules: # Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013 # # Top level modules: # Model Technology ModelSim ALTERA vcom 10.1e Compiler 2013.06 Jun 12 2013 # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # ** Error: (vcom-11) Could not find work.rts_data_transfer. # ** Error: ads1158_bfm_test_tb/simulation/submodules/ads1158_interface.vhd(39): (vcom-1195) Cannot find expanded name "work.rts_data_transfer". # ** Error: ads1158_bfm_test_tb/simulation/submodules/ads1158_interface.vhd(39): Unknown expanded name. # ** Error: ads1158_bfm_test_tb/simulation/submodules/ads1158_interface.vhd(41): VHDL Compiler exiting # ** Error: /opt/altera/14.0/modelsim_ase/linux/vcom failed. # Error in macro ./run_ads_1158_bfm_simulation.tcl line 9 # /opt/altera/14.0/modelsim_ase/linux/vcom failed. # while executing # "vcom "$QSYS_SIMDIR/submodules/ads1158_interface.vhd" -work ads1158_interface_0 ..." # ("eval" body line 8) # invoked from within # "com"  I really don't know, where I should point the modelsim software to into the filestructure that Qsys created by generating my BFM testbench.  I guess that modelsim complains that it does not find my little library file (that contains my systemwide constants). I don't know, how I can fix this issue and honestly, I don't know how to proceed from there if it is fixed.  I know from the examples that I need an additional program file that actualle calls the BFM API, but i don't know how to implement a small program that e.g. starts the clock of my testbench ticking.  Can somebody provide a little guidance on that? And of course a solution for the above shown modelsim error?  Thank you!  Maik

[Altera_Forum]

Hi Maik, 

 I've posted a couple of examples of how to use the Avalon-MM BFM. I always create a testbench separate from the one generated by Altera.  Take a read of this tutorial ...  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  and look at its forum thread: http://www.alteraforum.com/forum/showthread.php?t=34787  Things have changed slightly with 14.0, so I wrote an example in this thread; download qsys_vip.zip and follow the readme.txt (page 3 post# 25)  http://www.alteraforum.com/forum/showthread.php?t=32952&page=3  There's SystemVerilog tasks in the testbench for performing Avalon-MM read/write single/burst, which is pretty much all you need.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Thanks for your answer! I will look through that, tomorrow.  By the way, I solved my modelsim compilation error by changing the vhdl file order of the files of my component in Qsys. This made the compiling sucessfull, but I still have no idea how to apply the API calls. I hope I will find the right starting point in the links you provided.  Maik

[Altera_Forum]

Hi, again! 

 Okay, I couldn't resist an read the Qsys part of your tutorial pdf.  It looks quit good. Very nice writing an the steps are very clear. However, i did not found a hint to the API calls to control the BFMs. But maybe I have to check the source code of the testbench which I really will do tomorrow.  Any chance to make your tutorials also for VHDL?   Regards, Maik

[Altera_Forum]

--- Quote Start ---   Okay, I couldn't resist an read the Qsys part of your tutorial pdf.  It looks quit good. Very nice writing an the steps are very clear.   --- Quote End ---   Thanks!    --- Quote Start ---   However, i did not found a hint to the API calls to control the BFMs. But maybe I have to check the source code of the testbench which I really will do tomorrow.   --- Quote End ---   Yeah, the testbench code is pretty self-explanatory. The hard part was figuring out which SystemVerilog BFM routines needed to be called. The qsys_vip.zip has a working example, so ultimately you don't really care, you can just copy the read/write tasks (just copy the whole testbench and edit it).    --- Quote Start ---   Any chance to make your tutorials also for VHDL?    --- Quote End ---   The Verification suite did not used to have VHDL models, so I wrote my own BFM with limited Avalon-MM transaction support, so that I could test VHDL-only designs in Modelsim-ASE (single-language mode). Take a look at the code for this presentation ...  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111slides_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111slides_hawkins.zip   ESC-104Code_Hawkins\dsp_tutorial\vhdl\lib\packages\test\avalon_bfm_pkg.vhd   and then look at the VHDL testbench for the tutorial. Its a simple BFM relative to what the Verification IP Suite provides, but its good enough :)  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 firstly, pretty interesting stuff that you are working on. I think I can use some of this DSP information, too, in my future work. Thanks for providing this!  Second, I succesfully simulated your LED/Button PIO Design using the verilog approach according to your tutorial. This is EXACTLY what I would like to implement for my own design.  This brings me to the third point: My VHDL problem. Unfortunately, I did not find your "avalon_bfm_pkg.vhd" file that I'm really keen on to look into! It seems not to be contained in any of the links you provided. I also looked a little bit around your Website but had no luck there, too (besides finding other interesting stuff . . . ).  I really would go with your Verilog testbench that stimulates the avalon mm master bfm and I would adjust that to my component, but since I use Modelsim ASE, I have no chance to use mixed language simulation.  In the latest Quartus version (14) there seems to be full VHDL support for the Avalon (and AXI) BFMs. Is there any chance that one (maybe you?!? ;-) ) could take the qsys_system of your tutorial, generates it with VHDL simulation model and builds a little VHDL BFM testbench that feeds the Qsys generated simulation model with some stimulus like you did it with your verilog testbench?  I tried to analyze your verilog code in order to understand how you used the BFM API. I found out that you have this "object" .BFM, on which you call `BFM.init();. I really have no idea what I have to do to implement something similar in a VHDL testbench. The next thing is how you use those "avalon_write()" and "avalon_read()" functions. How do I implement those calls in VHDL. Next thing is that I don't know if theis $display() command is something verilog specific, or if it is command that modelsim uses. What kind of packages or libraries do I have to import in a VHDL testbench so that I can achive the same resutls with your verilog testbench. Your qsys_system_dut port definition does only contain ports of the components for the components that are under test (like the LED PIO and the Buttzon PIO), but none for the master BFM. How do the BFM API calls "know" what their destination is?  etc.etc.  @edit: What I additionally would like to mention is that I of course looked at the VHDL example used in the "Avalon Verification IP Suite" user guide. I have to say that these files " test_program_pkg.vhd" and "test_program.vhd" totally overwhelmed me. I just don't know where to find the essential stuff that I basically need and from what I can start to extend the testbench accoring to my needs.  Maybe you can give me some hints, or provide the full link to your VHDL testbench if this answers a lot of my questions, already.  One thing about this VHDL testbench: You wrote that you "wrote your own BFM". So that means that it is not based on the Avalon Verification IP API, right? Because using this API would be my final goal for testing of my design.  Thanks again for your kind help!  Regards, Maik

[Altera_Forum]

Hi again, 

 I was able to combine your tutorial qsys_system (compiled as VHDL simulation model) with the above mentioned "test_program_pkg.vhd" and "test_program.vhd" and an additional tb.vhd file also derived from the "Avalon Verification IP Suite" user guide tutorial. It all compiled in modelsim and when I run the simulation, at least, the clock is ticking :-) . . . . . This is easy to understand (also for me) because the clock is generated in the tb.vhd file that has the qsys_system instantiated it as component and (via portmapping) provided this clock to the component.  Now, I wanted to use the test_program.vhd to provide some stimulus to the master bfm. But I fear that something is missing in order to connect the test_program.vhd with the qsys_system.vhd.  I uploaded my project that is based on your tutorial as zip file. I added the above mentioned testbench files. Maybe somebody has an idea how I can get this running to get nearly the same results like I get if I run the verilog simulation provided by Dave.  Thanks, Maik

[Altera_Forum]

--- Quote Start ---   This brings me to the third point: My VHDL problem. Unfortunately, I did not find your "avalon_bfm_pkg.vhd" file that I'm really keen on to look into! It seems not to be contained in any of the links you provided. I also looked a little bit around your Website but had no luck there, too (besides finding other interesting stuff . . . ).   --- Quote End ---   Oops, the last link above should have been to the code zip file, not the slides ...  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-104code_hawkins.zip    --- Quote Start ---   I really would go with your Verilog testbench that stimulates the avalon mm master bfm and I would adjust that to my component, but since I use Modelsim ASE, I have no chance to use mixed language simulation.   --- Quote End ---   Ok.    --- Quote Start ---   In the latest Quartus version (14) there seems to be full VHDL support for the Avalon (and AXI) BFMs. Is there any chance that one (maybe you?!? ;-) ) could take the qsys_system of your tutorial, generates it with VHDL simulation model and builds a little VHDL BFM testbench that feeds the Qsys generated simulation model with some stimulus like you did it with your verilog testbench?   --- Quote End ---   That is my plan, when I update the tutorial, but I've been too busy :)    --- Quote Start ---   I tried to analyze your verilog code in order to understand how you used the BFM API. I found out that you have this "object" .BFM, on which you call `BFM.init();. I really have no idea what I have to do to implement something similar in a VHDL testbench.   --- Quote End ---   This is where the difference in Verilog and VHDL shows. In Verilog you can "reach down into" the design using a hierarchical path. You can now do this in VHDL-2008, but I haven't tried using it. The "proper" way to do this in VHDL is to use a BFM I/O object (created using a record and a resolution function). Altera have chosen to go the "hacked" route for their VHDL BFM support in that they have defined a global signal within a package and then provide their BFM functions with a BFM master index ... in my opinion an ugly solution.    --- Quote Start ---   The next thing is how you use those "avalon_write()" and "avalon_read()" functions. How do I implement those calls in VHDL.   --- Quote End ---   Use the VHDL BFM I wrote, it should be good enough to test your own custom VHDL components,    --- Quote Start ---   Next thing is that I don't know if theis $display() command is something verilog specific, or if it is command that modelsim uses.   --- Quote End ---   Its a Verilog task provided by the simulator. Look at my VHDL testbench and you'll find a log_pkg.vhd with logging functions.    --- Quote Start ---   What kind of packages or libraries do I have to import in a VHDL testbench so that I can achive the same resutls with your verilog testbench.   --- Quote End ---   The DSP code uses VHDL, so look at its testbenches. I wrote a really basic Modelsim testbench in a couple of other threads too ...  http://www.alteraforum.com/forum/showthread.php?t=45770 http://www.alteraforum.com/forum/showthread.php?t=32386  These don't include the BFM, but they have examples of the logging procedures.    --- Quote Start ---   Your qsys_system_dut port definition does only contain ports of the components for the components that are under test (like the LED PIO and the Buttzon PIO), but none for the master BFM. How do the BFM API calls "know" what their destination is?   --- Quote End ---   Read the source code. `BFM is defined at the top of the testbench as the path to the BFM component. When the testbench code calls `BFM.<some function>, the function definition is inside the BFM Verilog that was added into the Qsys system.     --- Quote Start ---   What I additionally would like to mention is that I of course looked at the VHDL example used in the "Avalon Verification IP Suite" user guide. I have to say that these files " test_program_pkg.vhd" and "test_program.vhd" totally overwhelmed me. I just don't know where to find the essential stuff that I basically need and from what I can start to extend the testbench accoring to my needs.   --- Quote End ---   Take a look at my simplified code, and if you don't like it, and pester me enough, I'll take a look at Altera's VHDL support to see if its worth using.    --- Quote Start ---   Maybe you can give me some hints, or provide the full link to your VHDL testbench if this answers a lot of my questions, already.  One thing about this VHDL testbench: You wrote that you "wrote your own BFM". So that means that it is not based on the Avalon Verification IP API, right? Because using this API would be my final goal for testing of my design.   --- Quote End ---   It depends what features of the Altera API you want. Personally Avalon-MM read/write burst/single was enough for my needs.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 thanks again for your very good answer! This helps alot.  I found the BFMs and will try them as soon as possible. I already saw that you used avalon read/write signals as active high, whereas I use them active low. But since this is VHDL, I have no problems tweaking them to my needs. . . .     --- Quote Start ---  It depends what features of the Altera API you want. Personally Avalon-MM read/write burst/single was enough for my needs.  --- Quote End ---    The feature I need is that I'm able to simulate my Qsys system just the way it behaves like if it is connected to the HPS of a Cyclone V device.  Right now, my main problem is the adressing of registers inside my components. If I want to address subsequent registers of my components from the HPS, I have to increment the HPS address by 4. Additionally, I have implemented an Avalom MM Master in my Qsys system that runs "free", say without any connection to the HPS and reads data out of avalon MM slaves of my custom components in order to serialize them and stream them via the DMA of the HPS to the Linux system on the HPS. Anyway, this master component also has to increase the addresses by 4 if it wants to read subsequent data words out of my components. Right now, I simulate my data transfers with hand written testbenches that lack the interconnet logic of the Avalon bus. In my testbenches I have to increment the address by 1 if I would like to read subsequent data from my components. So I have to "adjust" something in my test models in order to simulate. But if I do this, I do not test the system anymore that will finally run in the finished design. What I also think is a neat feature of the BFMs is that it is integrated in Qsys. All interconnect logic between the Avalon bus and my component would be done by qsys instead of me "wiring" all those signals together.  From the first glance at your BFMs I cannot tell, if they fit my above mentioned requirements/wishes. Maybe you can answer that in a sentence, or two.  Regards, Maik

[Altera_Forum]

--- Quote Start ---   The feature I need is that I'm able to simulate my Qsys system just the way it behaves like if it is connected to the HPS of a Cyclone V device.   --- Quote End ---   As a practical matter, I think the HPS system uses AXI, so if you are creating Avalon-MM slaves, Qsys will insert AXI to Avalon-MM conversion logic. However, as far as simulation and verification goes, using an Avalon-MM BFM to test Avalon-MM slaves is just fine.    --- Quote Start ---   Right now, my main problem is the addressing of registers inside my components. If I want to address subsequent registers of my components from the HPS, I have to increment the HPS address by 4. Additionally, I have implemented an Avalom MM Master in my Qsys system that runs "free", say without any connection to the HPS and reads data out of avalon MM slaves of my custom components in order to serialize them and stream them via the DMA of the HPS to the Linux system on the HPS. Anyway, this master component also has to increase the addresses by 4 if it wants to read subsequent data words out of my components.   --- Quote End ---   That is to be expected; read the Avalon-MM Interface Specification (again). Avalon-MM masters use "byte addressing", whereas slaves use "word addressing", so an Avalon-MM master accessing a 32-bit Avalon-MM slave 32-bits at a time, needs to increment its (byte-based) address by 4-bytes each time.    --- Quote Start ---   Right now, I simulate my data transfers with hand written testbenches that lack the interconnet logic of the Avalon bus. In my testbenches I have to increment the address by 1 if I would like to read subsequent data from my components. So I have to "adjust" something in my test models in order to simulate. But if I do this, I do not test the system anymore that will finally run in the finished design.   --- Quote End ---   In my point-to-point testbenches I connect the byte-based address to the master, then drop the LSBs and connect the word based address to the slave, and then add a note that this corresponds to the job of the non-existent Avalon-MM fabric.    --- Quote Start ---   What I also think is a neat feature of the BFMs is that it is integrated in Qsys.    --- Quote End ---   Yep, that is why I use it.    --- Quote Start ---   From the first glance at your BFMs I cannot tell, if they fit my above mentioned requirements/wishes. Maybe you can answer that in a sentence, or two.   --- Quote End ---   They do. Qsys is dumb though and does not handle records as top-level I/O ports. To use my BFM with a Qsys system, you basically export a master interface, and then connect the BFM outside the Qsys system. Its a simple work-around.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  In my point-to-point testbenches I connect the byte-based address to the master, then drop the LSBs and connect the word based address to the slave, and then add a note that this corresponds to the job of the non-existent Avalon-MM fabric.  --- Quote End ---    This seems to be a suitable way..... I read that avalon spec a couple of times during the last years but it seems as if I am always missing something.....  One last question before I start using those BFMs of yours: I asume that it is possible to implement an avalon busstructure, where I provide the aforementinoed avalon master and two avalon slave (the data source and the data sink) components and connect those with your BFMs, right. This data transfer between my avalon master and slave components is something I have to heavy test because in there I somwhere have a bad bug that is annoying to search in the real system with signal tap.  Thanks, Maik

[Altera_Forum]

--- Quote Start ---   One last question before I start using those BFMs of yours: I asume that it is possible to implement an avalon busstructure, where I provide the aforementinoed avalon master and two avalon slave (the data source and the data sink) components and connect those with your BFMs, right. This data transfer between my avalon master and slave components is something I have to heavy test because in there I somwhere have a bad bug that is annoying to search in the real system with signal tap.   --- Quote End ---   Create a Qsys system, so that you know you are testing Altera's Avalon-MM fabric;  1. Add your Avalon-MM slaves 2. Export an Avalon-MM master interface (I forget how to do this, but I'm pretty sure there is an option in the Qsys GUI now, previously I just created a basic _hw.tcl file)  Save that and generate a VHDL simulation model. Your testbench can then;  1. Instantiate the Qsys system 2. Connect the BFM master to the exported master interface 3. Connect the BFM server and testcase generator  Model your code after:  ESC-104Code_Hawkins\dsp_tutorial\vhdl\lib\altera_avalon\test\avalon_bfm_tb.vhd  where the Avalon-MM slave register is replaced with your Qsys system, and the Avalon-MM signals from the BFM server connect to the master ports exported on the Qsys system.  Cheers, Dave

[Altera_Forum]

Hi Maik, 

 Sorry, I can't help you for a few days, as I'll be traveling. Ping me on Friday if you're still stuck.   If your questions are related to the VHDL verification suite functions, file a Service Request with Altera and get some direct/official help.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 just for information: I filed a SR to Altera 3 days ago. No answer, yet . . . .   At least, our discussion and your tutorial opened my mind for the fact that I can use the Qsys simulation model for the simulation of my custom master that is connected to 2 of my custom slave components. The model from Qsys contains all the interconnect, so that i was able to fix a lot of my problems until now. Since the master runs "free" without configuration, I just needed to put one of the slaves in simulation mode, which I did the old way by just writing some avalon transfers in my testbench file by hand. The same I did for the AXI read of the other slave . . . It is not nice, but it works for now.  If I get an answer for my SR, i will post some results, here, too.  Besides, I had a look at the VHDL-2008 additions and agree, that the hierarchical signal access looks quiet usable and it is a pitty that Altera has choosen the BFM ID approach for their verification API . . . .   Regards, Maik

[Altera_Forum]

Hi, 

 I just wanted to post a little update here about my findings about BFMs + VHDL.  I'm now able to play with the BFMs through VHDL. Basically what I do is:  1. I create a system in QSys with my custom Avalon MM Slave components thati would like to test. 2. I connect the slave interface to an instantiation of the Avalom MM Master BFM and configure it to my needs (bus withs, signal polarity, etc., etc.). 3. I export all conduits and the clock and reset signals from all components. 4. I let QSys generate the simulation model (in VHDL). 5. I use the run_simulation.tcl script taken from the "Introduction to Avalon Verification IP Suite User Guide"-example for simulations in modelsim. 5a. I adjust the variable "system_name" to my Qsys project name. 5b. I removed the test_prgram_pkg.vhd file compilation from the script in order to get rid of all the definitions that i don't understand, yet. 5c. I provide an own test_program.vhd file where I just (until now) set up a basic Avalon write transfer like this: procedure avalon_write( address : in integer; data : in integer) is begin set_command_request(master_bfm.altera_avalon_mm_master_bfm_vhdl_pkg.REQ_WRITE, AVALON_MASTER_BFM_VHDL_ID, req_if); set_command_idle(0, 0, AVALON_MASTER_BFM_VHDL_ID, req_if); set_command_init_latency(0, AVALON_MASTER_BFM_VHDL_ID, req_if); set_command_address(address, AVALON_MASTER_BFM_VHDL_ID, req_if); set_command_data(data, 0, AVALON_MASTER_BFM_VHDL_ID, req_if); push_command(0, req_if); end procedure avalon_write; I use this procedure in the test_program.vhd file to initiate Avalon writes at certain events or times. As one can see, I tried to base this on Daves Veriog examples, since I think that these are nicely structured. I have problems still on waiting for responses in order to be sure that the transfer is finished since I never get a value of "1" as pending responses so that I'm in an endless loop if I do so. This is why I left this out here. (I wonder how one can get a response to a write transfer anyway?!?). 6. I provide a testbench tb.vhd file where I instatiate the Qsys system along with my test_program and where I generate clock and reset signals. 7. I do a "source run_simulation.tcl" in modeslim and voilà, I have the defined communication on the Avalon bus without all the overhead of the Altera provided examples that I do not fully understand.  As you can see, there are still questions left like why do I not get any response on my write transfer. Maybe somebody can answer this or I have to figure out myself ;-).  Regards, Maik