Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Avalon MM Slave - How to detect Interrupt acknowledgement from HPS on CYCLONE V

syam
Novice
‎05-04-2021 08:31 AM
1,092 Views

Hi

We have a system design in platform designer for CYCLONE V. We have a custom IP module to which we have added an Interrupt Sender interface. The interrupt receiver is on the HPS instantiated in the platform designer. Once this slave raises the IRQ how will it know that the HPS master has acknowledged / serviced the interrupt. Is there a register or bit line that the slave can read to figure this out. The best info on the documentation we found is given below. But this doesn't clarify the above query we have. 

syam_0-1620142138752.png

Best Regards

Syam

 

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EricMunYew_C_Intel
Moderator
‎05-31-2021 01:53 AM
1,054 Views

Avalon master will disasserting the irq line as acknowledgement.


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