Avalon-MM Template for setting registers

[Altera_Forum]

Hi, 

 does anyone have a VHDL/Qsys template for setting "registers" after the board powered up? A lot of Altera IP requires to set certain configuration parameters via the Avalon-MM interface, and using the NIOS II for that seems overkill to me (and takes the smoothness out of the design flow).  Cheers, Peter

[Altera_Forum]

Your question is a little vague. What board? And what do you mean by "registers"? If the registers are in the FPGA, then you can simply provide default values in your HDL code. 

 Explain what you'd like to do.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 In their IP, Altera calls the space where dynamic configuration parameters are saved "registers", and you can read and write those via the Avalon MM interface. I am sorry for the misunderstanding, I didn't mean to refer to actual registers, even though that's most likely the way how this is implemented internally. (I put that in quotes now in the initial post as well).  Cheers, Peter

[Altera_Forum]

Hi Peter, 

  --- Quote Start ---   In their IP, Altera calls the space where dynamic configuration parameters are saved "registers", and you can read and write those via the Avalon MM interface. I am sorry for the misunderstanding, I didn't mean to refer to actual registers, even though that's most likely the way how this is implemented internally. (I put that in quotes now in the initial post as well).   --- Quote End ---   You're still being too vague.   Altera has lots of IP, which one are you asking questions about?  Since you are asking about Altera IP, then the code is likely to be a black-box, i.e., you cannot simply change the power-on defaults for the registers. However, there is probably no need to. The power-on defaults are usually sane values for the Altera IP I have used.  You need to describe what IP you are using, and what it is you really want to do with it.  For example, if after the FPGA is configured, you need to access some registers to program/configure the IP, then you can use a NIOS II processor, or you can use a JTAG-to-Avalon-MM bridge and configure it via JTAG, or if your board has some other interfaces, you can use a control computer to access the FPGA, and have it change the registers.  Cheers, Dave