Avalon-MM pipeline bridge won't work with Stratix II devices

Altera_Forum · ‎07-28-2010

Hi all!

I have a pretty simple system

nios ii/f

main_mem

avalon_mm_pipeline_bridge

timer_sys_clk

sysid

jtag_uart

sgdma_tx

sgdma_rx

descriptor_memory

tse_mac

that runs nios ii ide "simple socket server" software example.

---------------

I had to migrate it on a new PCB board. The changes were the following:

DIFFERENT FPGA: changed device from [Stratix II GX] to [Stratix II]

hence DIFFERENT IOs: change top.vhd, QSF pin assignment, timing constraints

in particular different memory: changed main_mem controller from [DDR2 SDRAM High Performance Controller] to custom QDR controller

---------------

The thing is that this system no longer works.

I get the following error at startup:

--- Quote Start ---

InterNiche Portable TCP/IP, v3.1

prep_tse_mac 0

prepped 1 interface, initializing...

[tse_mac_init]

Error opening TX SGDMA

init error -22 on net[0]

mctest init called

IP address of : 192.168.1.80

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

INFO: iniche_init: Wait until NicheStack is ready...

INFO: iniche_init: NicheStack ready

--- Quote End ---

It turns out system works well if I remove the Avalon-MM pipeline bridge.

Any idea why???

Or maybe it comes from something else I changed in the QSF ?

Thanks

Altera_Forum · ‎07-28-2010

I think we would need to see your SoPC topology to help you. If you look at the driver for the TSE MAC you'll see where your error is coming from:

  /* Get the Rx and Tx SGDMA addresses */
   sgdma_tx_dev = alt_avalon_sgdma_open(tse_hw->tse_sgdma_tx);
   
   if(!sgdma_tx_dev) {
      dprintf(" Error opening TX SGDMA\n");
      return ENP_RESOURCE;
   }

Inidication is that the system can't see your SGDMA controller or that it hasn't been informed about it. Are you aware of the changes to the driver which require that you specify to the MAC the names of it's SGDMA controllers before initializing the NicheStack?

Jake

Altera_Forum · ‎07-28-2010

--- Quote Start ---

Are you aware of the changes to the driver which require that you specify to the MAC the names of it's SGDMA controllers before initializing the NicheStack?

--- Quote End ---

No. What do I have to do? Where?

Altera_Forum · ‎07-28-2010

Refer to the Software Programming Interface section (section 6) in the TSE user's guide.

http://www.altera.com/literature/ug/ug_ethernet.pdf

Jake

Altera_Forum · ‎07-30-2010

I could not find any explaination of my problem...

Addresses in system.h are correct (in avalon_mm_pipeline span).

Avalon-MM pipeline bridge is supposed to be transparent.

Software accesses a component described in system.h, CPU accesses the pipeline bridge, which relays the accesses to the corresponding component. Then the component 'answers' to the pipeline bridge that relays the answer to the CPU.

What I do not understand is that it works perfectly on the initial Stratix II GX project.