Hello, I'm using Avalon Streaming Interface in Qsys to connect my components and Altera IPs. In my testbench, I read a file and use a data format adapter in order to put 4 symbols per clock cycle in and get one symbol per clock cycle out. This data format adapter works fine, but I saw that it removes my eop signal. When the source components is sending the end of package signal, the data format adapter does not output it (like the start of package signal). This behaviour is strange, the valid signal is at the same time high. Does anyone know why this could happen? Thank you!
Simulation screenshot see attachments.
