Avalon multiple interfaces performance

[Altera_Forum]

Hello there. I am currently developing a generic data acquisition system which uses a Cyclone III FPGA. The internal tasks are divided in blocks, which are Avalon MM slaves. There is an Avalon MM master which is responsible for all the system's tasks, which include moving data from the ADC to be sent through an USB controller. 

 Recently I started noticing that the Avalon bus could get really busy at times when there is a lot of data to move around, and I started wondering if I could gain performance by adding a secondary Avalon master interface which could be exclusively used for transferring the captured data from the Avalon slave responsible for getting the data off the ADC (and putting it into FIFOs, maybe this interface could be burst capable), while another master interface could carry on with a number of other simultaneous tasks as sending different data to other slaves in the system.  Is this good practice, can I do it, or would be best not to get so complicated and rely on one Avalon master bus to move all the data around?  Thanks in advance.

[Altera_Forum]

Designing a system with two busses can make your system go faster. You just need to balance it well so that both are used, but yes it should increase the througput, as if each master access a different slave at any given time, they will do it in parallel. 

Just be sure to use the correct master when needing to access a slave. There are other ways of optimizing an Avalon memory mapped bus usage, especially pipelinined transfers. With pipelining you can send several read or write requests without waiting for the result, and with systems that have a bit of latency it is a huge improvement. IIRC with the recent memory controllers it is as efficient as bursts and maybe easier to implement.

[Altera_Forum]

The fabric uses slave side arbitration so if you have multiple masters then as long as they don't access the same slave you can have multiple transfers occuring concurrently. This is because Avalon-MM isn't a bus, it's an interface standard built on top of a partially (or fully depending on your design) crossbar switch. 

 Don't bother using bursting for anything that doesn't require it. For example bursting into a FIFO doesn't make much sense since a FIFO doesn't require a burst to be fast. Use bursting for things that could use it like off-chip interfaces that require bursting to be efficient.   For what you are doing it sounds like you could use a streaming and memory mapped hybrid approach. Use streaming for the FIFO connections since by their very nature, FIFOs *are* just a stream of data. On the other side of your custom block you would read/write the stream to memory.   Take a look at the Qsys tutorial, you'll see something similar to what I'm talking about except instead of FIFOs the data stream are data pattern generators/checkers:   http://www.altera.com/support/examples/design-entry-tools/qsys/exm-qsys-tut.html

[Altera_Forum]

Will look into it, thanks