Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Bad code, but no error, will settle for warning :)

Altera_Forum
Honored Contributor II
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This code compiles(!). 

 

always @ (posedge clock ) begin  

state <= NextState;  

state <= state;  

state <= 0;  

end 

 

Using the SignalTap it appears that state gets set to 0. Apparently its valid code. Is there a way to at least get a warning out of this? 

 

Thank you, 

Steve
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Altera_Forum
Honored Contributor II
528 Views

Why would you want a warning for perfectly valid code? 

The user has to take some responsibility! 

 

You may want to invest in a linting tool.
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Altera_Forum
Honored Contributor II
528 Views

Indeed. Thanks so much

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Altera_Forum
Honored Contributor II
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I actually use that method when I want a default value on a signal. That way 'a' will always have a value even if I don't assign it in the if statement. 

 

always@(posedge clk) 

begin 

a <= 1'b0; 

if(something) 

begin 

a <= 1'b1; 

end 

else if(something else)  

begin 

<something that doesn't touch a> 

end 

end
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Altera_Forum
Honored Contributor II
528 Views

 

--- Quote Start ---  

I actually use that method when I want a default value on a signal. That way 'a' will always have a value even if I don't assign it in the if statement. 

 

end 

--- Quote End ---  

 

This seems like a good practice. Now I see the value of such a method.  

Thank you, 

Steve
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