Be confused with setup time slack calculation

Altera_Forum · ‎01-08-2008

In QuartusII Handbook 7.1, Page 1614, it listed setup time slack equation as below:

Clock Setup Slack = Data Required Time - Data Arrival Time

Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +

μtCO + Register-to-Register Delay

Data Reqiured = Clock Arrival Time – μtSU – Setup Uncertainty

Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register

When I study the timing report generated by TimeQuest, I find something different,

It seems that Data Required time is calculated by the following equation:

Data Reqiured = Clock Arrival Time + μtSU

Pls see the report information below:


Info: Path# 1: Setup slack is 2.131 
    Info: ===================================================================
    Info: From Node    : FreqMeasure_NiosII:inst|freqmeasure_wholesystem_inst:the_freqmeasure_wholesystem_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|FREQMeasure_SingleChannel:\U2:140:channel_x|FREQMeasure_PeriodCounterDuringStrobe:U2|s_cnt
    Info: To Node      : FreqMeasure_NiosII:inst|freqmeasure_wholesystem_inst:the_freqmeasure_wholesystem_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|FREQMeasure_SingleChannel:\U2:140:channel_x|FREQMeasure_PeriodCounterDuringStrobe:U2|s_cnt
    Info: Launch Clock : FreqMeasure_NiosII:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0
    Info: Latch Clock  : FreqMeasure_NiosII:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      0.000      0.000           launch edge time
    Info:      0.283      0.283  R        clock network delay
    Info:      0.587      0.304     uTco  
    Info: 
    .
    .
    .
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     10.000     10.000           latch edge time
    Info:     10.254      0.254  R        clock network delay
    Info:     10.294      0.040     uTsu  FreqMeasure_NiosII:inst|freqmeasure_wholesystem_inst:the_freqmeasure_wholesystem_inst|freqmeasure_wholesystem:the_freqmeasure_wholesystem|FREQMeasure_SingleChannel:\U2:140:channel_x|FREQMeasure_PeriodCounterDuringStrobe:U2|s_cnt
    Info: 
    Info: Data Arrival Time  :     8.163
    Info: Data Required Time :    10.294
    Info: Slack              :     2.131

I'm newer in timing analysis field, hope for help, thanks in advance.

Altera_Forum · ‎01-08-2008

The uTsu is subtracted from the Data Required time. You seem to have a negative uTsu value in the case you show. Thus, Required = 10.254 - -40ps = 10.294. Most often you will see the uTsu subtracted in the TimeQuest reports.

+----------------------------------------------------------------------------------+

; Data Required Path ;

+-------+--------+----+------+--------+------------------+-------------------------+

; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ;

+-------+--------+----+------+--------+------------------+-------------------------+

; 2.500 ; 2.500 ; ; ; ; ; latch edge time ;

; 2.500 ; 0.000 ; ; ; ; ; source latency ;

; 2.500 ; 0.000 ; ; ; 1 ; PIN_L22 ; clk ;

...

; 4.910 ; 0.000 ; ; ; ; ; clock uncertainty ;

; 4.831 ; -0.079 ; ; uTsu ; 1 ; FF_X52_Y24_N29 ; out_reg[6][7] ;

+-------+--------+----+------+--------+------------------+-------------------------+

Altera_Forum · ‎01-09-2008

So negative uTsu is reasonable??? Sorry for the stupid question.

Altera_Forum · ‎01-09-2008

Someone else asked about negative tsu at http://www.alteraforum.com/forum/showthread.php?t=1679. tsu at a device input pin ("port" in SDC terminology) can easily be negative, but I don't remember noticing negative micro tsu before (the tsu right at the internal register). Maybe it's common.