Beginner question about making a beep sound

[Altera_Forum]

I am so sorry to ask such a simple question, which i have been thinking for whole night already. 

Here are the codes  module music(clk, speaker); input clk; output speaker;  reg [15:0] counter; always @(posedge clk) counter <= counter+1;  assign speaker = counter[15]; endmodule  [/B][/B][/B][/B][/B][/B][/B][/B]My question is : 1. Anyone can explain the logic to me. I very a beginner. 2. " always@(posedge clk) counter <= counter+1;" means it has positive clock only when counter is smaller than counter +1, but what is counter physically in this case??  3. Assign speaker to one of the value of counter is understandable, however, why then the speak will make a sound of frequency 381Hz if the input clock is set to be 25MHz, i know it's from 25MHz/65536= 381Hz, but i just dont understand why. how come? what is happening here?   Anyone can explain this? i will appreciate that. Thank you so much:oops:

[Altera_Forum]

<= is the assignment function. so it increments the counter by 1 on every positive edge of the clock. 

 The speed is because thats the toggling frequency of bit 15.

[Altera_Forum]

i have been to asked to use altera for programming in verilog HDL 

i want to know the basics of how to consruct schematic and execute please anyone help  regards h g rashmi

[Altera_Forum]

--- Quote Start ---  i have been to asked to use altera for programming in verilog HDL i want to know the basics of how to consruct schematic and execute please anyone help  regards h g rashmi  --- Quote End ---    I suggest you start your own thread, rather than hijacking other threads.