Behavioral vs Dataflow/RTL

[Altera_Forum]

Hello,  

 I am having some trouble identifying the differenace between behavioral and dataflow modelling. I have searched a bit on the internet and i have seen that these two coding styles are quite the same.   with regards to the entity decleration, it has to be the same for every coding style(inc. structural)   but then with structural modelling the architecture is defined using logic gates while with behavioral and dataflow they both use a process and it basically defines the function in terms of the inputs and outputs declared in the entity.   any help is appreciated :)

[Altera_Forum]

And also, in a structural model, if we define the inputs and outputs of our system in the entity and then in the architecture, we declare components and signals and then we instantiate the components and using the signals we connect everything together. 

 If we did this, it still wouldn't work because the functions of each components haven't been define and for example to define an and gate we say a <= b and c which is dataflow/behavioral coding style.   so basically even structural modelling isn't purely structural no?

[Altera_Forum]

It can be - components dont have to map to VHDL - they could be verilog code or netlists. A component just defines the interface to some other block. If the other block is VHDL, then components are not needed as you can do direct instantiation. 

As for behavioural or data flow - I think all the code you see that is synthesisable in VHDL is behavioural modelling. Dataflow modelling would not map to an FPGA and is often what you can use in testbenches.