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Altera_Forum
Honored Contributor I
2,206 Views

Best practice to define bidirectional pin in top level design file with Quartus II?

Being new to Quartus II and still in the phase to build some simple tests 

I used the Pin planner to define a bidirectional pin. 

 

This resulted in the following top level design file test1_top.v:  

 

module test1_top ( IO1 ); inout IO1; endmodule 

 

Compiling this leads to the following warning: 

 

warning (169064): following 1 pins have no output enable or a gnd or vcc output enable - later changes to this connectivity may 

change fitting results info (169065): pin io1 has a permanently disabled output enable 

 

Now I added another node 'IO1_OE' (also using pin planner): 

 

 

module test1_top ( IO1, IO1_OE ); inout IO1; assign IO1 = (IO1_OE == 0) ? 1'b1 : 1'bZ; endmodule 

 

But now I get the following warning: 

 

critical warning (169085): no exact pin location assignment(s) for 1 pins of 2 total pins. for the list of pins please refer to the i/o assignment warnings table in the fitter report. 

 

so the final question is: how do i correctly create (and use) a bidirectional pin in the top level module using quartus?
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2 Replies
Altera_Forum
Honored Contributor I
315 Views

The first warning occurs if you define a bidirectional pin, but don't use it bidirectionally. 

 

The second warning occurs because you apparently did not define both pins in the pin planner. 

 

Hint: A design that doesn't drive all output pins by actual logic or has unconnected input pins will always generate some warnings. You should write a useful and complete module definition, e.g. the model of a unidirectional or bidirectional tri-state driver.
Altera_Forum
Honored Contributor I
315 Views

Thanks alot! 

 

Simply using the bidirectional pin did the trick!# -)
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