CPU uasge by the fitter

[Altera_Forum]

Hi 

I am using quartus 9.0 . When i run qaurtus on 4 core processor , the fitter summary report that it is using only 1.6 . Thus the amout of time required to compile is 40 min. Is there a way to increase the processos usage . The option "use all processors" is also set.   Thanks  AVINASH

[Altera_Forum]

--- Quote Start ---  Hi I am using quartus 9.0 . When i run qaurtus on 4 core processor , the fitter summary report that it is using only 1.6 . Thus the amout of time required to compile is 40 min. Is there a way to increase the processos usage . The option "use all processors" is also set.   Thanks  AVINASH  --- Quote End ---    Hi Avinash,  not all fitting tasks could run in parallel. I would assume that setting to "use all processors" will not change the average usage. Did you run other programms on your QuadCore PC during fitting ? Maybe the average usage of processors could be increase by the use of design partitions.  Kind regards  GPK

[Altera_Forum]

Hi GPK 

 I made design parition for some modules with post-fit(strict) Netlsit type . Then i changed in non partition module and recompiled , then the partition merging is happening quikly , but the fitter is taking tha same time as earlier and thus the total time taken still remain the same, there is no reduction in the compile time. So is there a way to reduce the compile time? The design need to be recomplied many time so need to reduce the complie time.   Thanks AVINASH

[Altera_Forum]

--- Quote Start ---  Hi GPK  I made design parition for some modules with post-fit(strict) Netlsit type . Then i changed in non partition module and recompiled , then the partition merging is happening quikly , but the fitter is taking tha same time as earlier and thus the total time taken still remain the same, there is no reduction in the compile time. So is there a way to reduce the compile time? The design need to be recomplied many time so need to reduce the complie time.   Thanks AVINASH  --- Quote End ---    what kind of "Fitter Preservation Level" did you set for your design partitions ?   Kind regards  GPK

[Altera_Forum]

placement, routing and high speed tiles

[Altera_Forum]

--- Quote Start ---  Hi I am using quartus 9.0 . When i run qaurtus on 4 core processor , the fitter summary report that it is using only 1.6 . Thus the amout of time required to compile is 40 min. Is there a way to increase the processos usage . The option "use all processors" is also set.   Thanks  AVINASH  --- Quote End ---    Hi Avinash,  Not all algorithms in Quartus can take advantage of multiple processors. The processor usage you get will depend on your particular circuit. In general, very large designs (those that take hours to map or fit) will see a larger relative benefit than smaller designs, though there's a lot of variation.  Cheers,  Adrian Ludwin Altera Corp.

[Altera_Forum]

Hi Adrian  

 I made design parition for some modules with post-fit(strict) Netlist type and fitter preservation level as placement routing and high speed tiles . Then i changed in non partition module and recompiled , then the partition merging is happening quikly , but the fitter is taking tha same time as earlier and thus the total time taken still remain the same, there is no reduction in the compile time. So is there a way to reduce the compile time? The design need to be recomplied many time so need to reduce the complie time.  regards AVINASH

[Altera_Forum]

--- Quote Start ---  Hi Adrian    I made design parition for some modules with post-fit(strict) Netlist type and fitter preservation level as placement routing and high speed tiles . Then i changed in non partition module and recompiled , then the partition merging is happening quikly , but the fitter is taking tha same time as earlier and thus the total time taken still remain the same, there is no reduction in the compile time. So is there a way to reduce the compile time? The design need to be recomplied many time so need to reduce the complie time.  regards AVINASH  --- Quote End ---    Personally, I work more on parallel stuff than on incremental compile, so I can't help that much. Did you floorplan your design with LogicLock regions? My only suggestions would be to read the handbook chapter on incremental compilation and carefully read the info messages from the Fitter.   Cheers, Adrian Ludwin Altera Corp.

[Altera_Forum]

Ok  

 Thanks AVINASH