CYCLONE V SX, 400Mbps LVDS DDR Interface with DDR or SERDES, timing problems

[cooperd]

Hi all,

I am struggling and need to know how best to constrain Quartus to fit my design.

I am interfacing to a 200Msps, 14 bit  ADC using 7 DDR LVDS lines. This makes each LVDS line 400Mbit per sec. First I tried the LVDS SERDES with J=2 but that gave me timing errors as I found out the LVDS SEREDES does not use the dedicated SERDES circuitry for j=1 or 2.

So now I am trying J=4 and only using half the bits from the SERDES.

I have used the internal pll of the SEREDES and plan to use the clock phase shift to optimise the RSKM

I get timing errors no matter what I do. The errors are in the path between the receive buffers and the RX registers and seem to be down to a difference in data paths between the different bits.

Device is a CYCLONE V SX speed grade C8.

I have tried constraining the design in the sdc file but I do not think I am doing it correctly. Please can anyone help?

Thanks

Dave

Below is the section from my sdc file

#*************************************************************
# ADC
# 1. LVDS SERDES Transmitter/Receiver IP Cores User Guide 683062 | 2017.12.15
# Send Feedback LVDS SERDES Transmitter / Receiver IP Cores User Guide 45
#*************************************************************
create_clock -name virtual_clock_lvds -period 5

set_input_delay -clock [get_clocks virtual_clock_lvds] -max 0.5 [get_ports {LVDS_RX[*]}] -add_delay
set_input_delay -clock [get_clocks virtual_clock_lvds] -min -0.5 [get_ports {LVDS_RX[*]}] -add_delay

# Set false paths to remove irrelevant setup and hold analysis
set_false_path -fall_from [get_clocks virtual_clock_lvds] -rise_to [get_clocks ADC_DCLK] -setup
set_false_path -rise_from [get_clocks virtual_clock_lvds] -fall_to [get_clocks ADC_DCLK] -setup
set_false_path -fall_from [get_clocks virtual_clock_lvds] -rise_to [get_clocks ADC_DCLK] -hold
set_false_path -rise_from [get_clocks virtual_clock_lvds] -fall_to [get_clocks ADC_DCLK] -hold

# Set multicycle paths as we are running the LVDS at twice the actual data rate to enable Quartus to use the SERDES logic in the FPGA
set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -setup -end 2
set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -hold -start 2

[Kenny_Tan]

Do you mind to send us your design for investigation? We would like to see where is your timing violation that you are facing.

[Kenny_Tan]

Not sure if you have update on the above?

[cooperd]

Hi Kenny, I am not in the office today. I will send you the design tomorrow. It is large so I will send a link to a .qar file. I am compiling using 18.1.1.

Thanks

[ShengN_Intel]

Hi,

Understood that. Will wait for the design link.

Thanks,

Regards,

Sheng

[ShengN_Intel]

Hi @cooperd ,

I had checked the design provided. Check this document link https://www.intel.com/content/www/us/en/docs/programmable/683801/current/high-speed-i-o-specifications.html, the max rate for receiver data rate with SERDES factor J =4 to 10 is 640Mbps. Try to set that input data rate from 800Mbps to 600Mbps in order to get clock frequency of 200Mhz. Also, the positive RSKM.

The multicycle path needs one more cycle for example like below (Remember to use same -end/-start for both setup and hold):

set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -setup -end 3

set_multicycle_path -from {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|sd*} -to {acquire:inst1|ADS4249ADCIF:inst32|adcif:adcif_inst_0|altlvds_rx:ALTLVDS_RX_component|adcif_lvds_rx:auto_generated|rxreg[*]} -hold -end 2

Thanks,

Regards,

Sheng