Can EDIF Instantiated Entity be Defined by Subdesign During Compile?

[Altera_Forum]

I have an EDIF netlist export of a design which uses parts that do not directly map to Altera primitive functions. Is it possible to build a subdesign with Altera functions that would implement the function and be used to define the EDIF entity during compilation. 

 For example:   A T-Flip Flop in the circuit used to generate an EDIF netlist has the following ports.    (cell TFR  (cellType generic)  (comment "From OrCAD library STA_STD.OLB")  (view NetlistView  (viewType netlist)  (interface  (port VDD (direction INPUT))  (port GND (direction INPUT))  (port C (direction INPUT))  (port CB (direction INPUT))  (port R (direction INPUT))  (port Q (direction OUTPUT))  (port QB (direction OUTPUT))))))   An Altera T-Flip Flop does not have ports for VDD, GND, CB, R(active high), or QB. The additional functions would have to be defined in a subdesign or module.   Can a subdesign defined in terms of Altera functions be used during compilation to define an entity in the EDIF netlist?   Thanks, Eric

[Altera_Forum]

If Quartus is giving you an error for undefined entity for these things in the EDIF file, then I expect what you want to do will work. It would be just like having an .edf or .vqm from a third-party synthesis tool that targeted an Altera device but had a black box for something to be implemented in a source file to be synthesized directly by Quartus. This is typically done for black boxing a megafunction, but it should work for your own custom implementation of these primitives.

[Altera_Forum]

--- Quote Start ---  ... Altera primitive functions...  An Altera T-Flip Flop does not have ports for VDD, GND, CB, R(active high), or QB. The additional functions would have to be defined in a subdesign or module.   Can a subdesign defined in terms of Altera functions be used during compilation to define an entity in the EDIF netlist?  --- Quote End ---     I wouldn't try to find an Altera primitive that corresponds to the thing in the EDIF file. I'd use a simple HDL file with an RTL description written in a standard style that will synthesize D flip flops. (The actual registers in the device are D flip flops.)

[Altera_Forum]

My goal is to use a MAXII CPLD to emulate an ASIC design. 

 I am hoping to fill in the "black box" with atoms or WYSIWYG primitives to control as much as possible, how close the synthesis will be to the original design.   In the case of the T-Flip Flop example above, how would I make a "black box" built with WYSIWYG primitives and make it available during compilation to define the entity "TFR"?   If I could understand how to take care of this one part, I believe it would teach a man to fish and feed the rest of his library.   Thanks, Eric

[Altera_Forum]

The documents I suggested at http://www.alteraforum.com/forum/showthread.php?p=19260 might be of use for your application, at least to give you an idea of what can be done with primitives.

[Altera_Forum]

Thank-you for the link, I went through the "Designing with Low-Level Primitives" User Guide as suggested. I can see at least some of the merits and disadvantages to this approach. It does seem to address my goal. 

 I know this is a very basic question, but how would you suggest to make a definition for the example part "TFR" that will get used during compilation for the TFR entity in the EDIF netlist. Does it get included as a library? If so, how.   I realize that I'm asking for a bit of a hand hold here. Unfortunately I'm swimming a little with having to learn a completely new development tool (Quartus II) and do something non-standard to get our EDIF netlist to work.   Regards, Eric