Can Quartus produce a netlist with hierarchical flattening disabled

[mauricetucke]

Is a way to produce a netlist with hierarchical flattening disabled, what settings are required to produce that? We tried finding a setting in the EDA Netlist writer that is a part of the Quartus synthesis flow that could do this but didn't find anything relevant.

Many Thanks

[SyafieqS]

Hi Tucker,

May I know what is hierarchical flattening? and why you want to disable it?  Is for better timing and optimization?

I assume this could be like design partition? 

[SyafieqS]

Any update from previous reply?