Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Can Quartus produce a netlist with hierarchical flattening disabled

mauricetucke
Beginner
246 Views

Is a way to produce a netlist with hierarchical flattening disabled, what settings are required to produce that? We tried finding a setting in the EDA Netlist writer that is a part of the Quartus synthesis flow that could do this but didn't find anything relevant.

Many Thanks

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2 Replies
SyafieqS
Moderator
189 Views

Hi Tucker,


May I know what is hierarchical flattening? and why you want to disable it?  Is for better timing and optimization?

I assume this could be like design partition? 


SyafieqS
Moderator
137 Views

Any update from previous reply?


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