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Altera_Forum
Honored Contributor I
1,200 Views

Can actual delays be implemented with .sdc constrains?

Hi,  

 

 

Can actual delays be implemented with .sdc constrains?  

I will try to explain what i want to achieve: 

Lets say i have PLL with two output clocks "pll_c0" and "pll_c1".  

"pll_c0" drives DDR output register which is connected to output pin "clkout" 

"pll_c1" drives DDR output register which is connected to dataout[4..0] pins.  

By changing "pll_c1" clock phase i can change Tco ("clkout" to whole dataout[4..0]).  

But is there something i can do to add even more delay to lets say single pin dataout[4]? 

I have tried to apply set_output_delay to each individual pins with different Tsu and Th times but while testing on hardware i dont see any difference.  

 

 

My .sdc looks like:  

 

 

# Base clocks create_clock -period 5 -name clk # PLL create_generated_clock -name pll_c0 -source ] -phase 0 ] create_generated_clock -name pll_c1 -source ] -phase 0 ] # Output clk pin create_generated_clock -name clkout -source .altgpio_bit_i|out_path_ddr.fr_out_data_ddio|dataout}] # Output constraints set_output_delay -max $Tsu -clock }] set_output_delay -min -$Th -clock }] set_output_delay -max $Tsu -clock -clock_fall }] -add_delay set_output_delay -min -$Th -clock -clock_fall }] -add_delay
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14 Replies
Altera_Forum
Honored Contributor I
53 Views

What device?  

The PLL won't phase-shift an output due to constraints, that has to be done manually. The PLL also drives a global clock tree to get to the dataout DDR, so there is no way for it to change that delay. What the fitter can do is modify the output delay chains in the IO cell to meet the timing requirements, which should work(and I have seen work many times). Go to the Fitter Report -> Delay Chain Summary and see what's going on.  

It might be that it's pegged to the highest or lowest delay chain value and therefore can't move them anymore. I've also seen cases where I'm only looking at one timing model and thinking it should do something else, but if I look across all timing models it turns out it's doing the right thing. (I've also seen a case where there was a bug and it just chose the wrong value. If you want, you can manually assign the delay chain values in the Assignment Editor)
Altera_Forum
Honored Contributor I
53 Views

 

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What device?  

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Cyclone IV, or MAX 10. 

 

 

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The PLL won't phase-shift an output due to constraints, that has to be done manually 

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Yes, ofcourse I understand that and I use for this purpose dynamic phase shift option. :) 

 

Can you explain how set_output_delay command in .sdc file relates to Delay Chain values? I have tried to set Delay chain values manualy but for now i can not understand how to set my .sdc file?
Altera_Forum
Honored Contributor I
53 Views

Let's say your setup relationship is 10ns and hold is 0ns. For simplicity, let's set the otuput -max/-min values at 0, meaning they don't do anything. This means your output delay can be anywhere between 0 and 10ns. Now if your -max value were changed to 10ns, the data needs to get out within 0ns. It will never do this, but will make sure the delay chains are as small as possible. Instead, let's say your -min value was 10 and max was 0, now you need to get data out in exactly 10ns, so the delay chains should be cranked up as high as possible. Those are obviously extreme/fake cases, but shows how it works.  

 

If you want to manually control it, I think it's the D5 Delay in the Assignment Editor.
Altera_Forum
Honored Contributor I
53 Views

I think it is better to describe set_output_delay as defined by Synopsis. 

min is the delay required from the latch edge and max is the delay required to the latch edge. Thus min equates with -tH of external device while max equates with +tSU 

of external device (assuming board level data delay = clock delay). Thus if we want early/late margin of data transition window then: 

 

early margin = negative of min delay figure 

late margin = clock period – max delay 

 

if both are zero we get early margin = 0 and late margin = clock period i.e. data can change anytime, in effect no requirement 

 

The delay figures given are just information and are then translated by fitter to whatever delays required within fpga.
Altera_Forum
Honored Contributor I
53 Views

Thank you all,  

 

Do only output Delay chain settings are affected by .sdc constrains? In Assigment editor for MAX 10 I am seeing that valid values for "Delay from Output Register to Output Pin" are 0 and 1. So there is only two options to play with. Does this mean that no matter what you do with your constrains you can not get more or less delay except only those two valid settings for Delay chain?
Altera_Forum
Honored Contributor I
53 Views

Hello Kaz, I need your help in calculating total Execution time for my code . Can you help me with this

Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

Thank you all,  

 

Do only output Delay chain settings are affected by .sdc constrains? In Assigment editor for MAX 10 I am seeing that valid values for "Delay from Output Register to Output Pin" are 0 and 1. So there is only two options to play with. Does this mean that no matter what you do with your constrains you can not get more or less delay except only those two valid settings for Delay chain? 

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I presume the fitter will have more options internally for routing delays between io register and its buffer. The setting of 0/1 is just an extra for user.
Altera_Forum
Honored Contributor I
53 Views

 

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Hello Kaz, I need your help in calculating total Execution time for my code . Can you help me with this 

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where is the code. It sounds like software and sorry that is not my area
Altera_Forum
Honored Contributor I
53 Views

 

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I presume the fitter will have more options internally for routing delays between io register and its buffer. The setting of 0/1 is just an extra for user. 

--- Quote End ---  

 

 

Now I am a bit confused. So how can I make fitter to delay specific bus bit? I am thinking to putting something like that: 

 

# For bus bit 0 set_output_delay -max 1.0 -clock }] set_output_delay -min -0.5 -clock }] set_output_delay -max 1.0 -clock -clock_fall }] -add_delay set_output_delay -min -0.5 -clock -clock_fall }] -add_delay # For bus bit 1 set_output_delay -max 0.5 -clock }] set_output_delay -min -1.0 -clock }] set_output_delay -max 0.5 -clock -clock_fall }] -add_delay set_output_delay -min -1.0 -clock -clock_fall }] -add_delay 

 

This should give 0.5ns more delay on dataout[1] bit?
Altera_Forum
Honored Contributor I
53 Views

The fitter does not follow exact figures when it closes on timing. 

Instead it tries to get a timing pass and stop. At best it targets balanced tSU/tH slack
Altera_Forum
Honored Contributor I
53 Views

But it should try get more Tsu time in dataout[0] and more Th time in dataout[1]?  

 

Is my understanding correct that with these constrains I am saying that i want dataout[0] valid 1ns before clkout and 0.5 ns after? 

 

# For bus bit 0 set_output_delay -max 1.0 -clock }] set_output_delay -min -0.5 -clock }] set_output_delay -max 1.0 -clock -clock_fall }] -add_delay set_output_delay -min -0.5 -clock -clock_fall }] -add_delay 

 

And with these lines i want dataout[1] valid 0.5ns before clkout and 1 ns after? 

 

# For bus bit 1 set_output_delay -max 0.5 -clock }] set_output_delay -min -1.0 -clock }] set_output_delay -max 0.5 -clock -clock_fall }] -add_delay set_output_delay -min -1.0 -clock -clock_fall }] -add_delay 

 

If my constrains correct then in dataout[0] case fitter should try to make less delay to achieve positive slac on Tsu requirement and Th requirement should require less effort? 

For dataout[1] fitter should try to add more delay to achieve Th requirement and Tsu requirement should require less effort?
Altera_Forum
Honored Contributor I
53 Views

your interpretation of valid window is correct in both cases 

The tool does not care about comparing these values. It just wants to pass timing and it sees wide transition window available 

In short sdc is not meant for fine tuning of delays. 

I don't see why you need that
Altera_Forum
Honored Contributor I
53 Views

 

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I don't see why you need that 

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There is some hardware issues in system i use. FPGA is connected to external device - IC. We have equally matched short PCB traces connecting FPGA and external IC. Due to some issues in external device some bus bits has to be delayed more then others in order to capture them correctly in external device. So as a workaround I want to implement separate delays for each bus bit in FPGA. And I need a suggestion on how to do that.
Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

 

There is some hardware issues in system i use. FPGA is connected to external device - IC. We have equally matched short PCB traces connecting FPGA and external IC. Due to some issues in external device some bus bits has to be delayed more then others in order to capture them correctly in external device. So as a workaround I want to implement separate delays for each bus bit in FPGA. And I need a suggestion on how to do that. 

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For that purpose I will set the set_output_delay constraints per each bit based on its required valid window and leave that to the timing tool to see if it passes io timing. If it doesn't pass timing then you might look at other command options such as set_net_delay (though I don't use it). I assume your IF is source synchronous and that you are using fast output registers.
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