We are using a Quartus 13.0 with a Cyclone IV E family device that has 20 global clock/nets available on it. According to the Pin Planner we have some signals defined on the global pins A11, B11, B12, G22, T1, T2, T21, T22, AA11, AA12, AB11, AB12 and the global clock pins on A12, G1, and G21 are open. In the assignment editor we have some nets defined as global that are not physically connected to the global pins and what happens during a compile is that the nets connected to the physical pins automatically promoted to global clock assignments and the assignments to the nets not physically connected are ignored. This has the effect of complicating our route and fit because high fan-out nets assigned to a global attribute are being ignored in the assignment editor in favor of the physically connected nets on the global pins. Is there a way to force the compiler to adhere to the selections made in the assignment editor for the global clock settings and ignore the physically connected net names? Any help you can provide would be very helpful.
Physically, the global clock networks can be driven by dedicated clock pins, by PLLs or by user logic.They can not be driven by regular I/O pins. However, since they can be driven by users logic, there's a possible work around. Instead of assigning "signal_I_wish_to_be_global" to pin XX11, use lcell helper_cell (.in(helper_signal) .out(signal_I_with_to_be_global)) and assign "helper_signal" to pin XX11 instead. This will increase the pin to signal delay, but it will allow Quartus to use a global network.