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Can't get Qsys to generate a testbench for a custom component using exported signals

Altera_Forum
Honored Contributor II
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I’m trying to use Qsys 13.1 to generate a testbench for a custom component that uses one Avalon Slave interface and one conduit to export 4 signals. I know the component works, I use it in an existing design, I'm just trying to come up to speed on Qsys generated test benches. 

 

I add my component as the sole component in a new Qsys system and export all the interfaces (clk, reset, avalon_save, conduit). 

 

When I generate the testbench it throws an error “Error: TB_Gen: Design has 4 but instance has 0 exported interface” 

 

If this worked, I thought it would attach an Altera Conduit BFM to the conduit interface of my component in the generated test bench.With that assumption, I tried piecing together the test bench by hand but when I connect the Conduit BFM to my conduit_end interface, it complains that they need to be on the same clock and reset domain, but the Conduit BFM doesn’t have a clock or reset interface. 

 

 

 

This seems like a simple thing that most everybody using a testbench would want to do frequently.The only tutorials that I’ve found use a FIFO or some other Altera component as a DUT which doesn’t export any signals. 

 

 

 

Can anyone point me to an example that could enlighten me on this subject? 

 

Thanks for your time! 

 

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Altera_Forum
Honored Contributor II
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Your understanding/expectations all sound correct. I just tried it with one of my components with 13.1 Web Edition and it works fine basically as you wrote (new system, delete the default clk, add my component, export all interfaces including clk and reset, "Generate..." with Standard BFM's added).  

 

For what it's worth, I do have some old components (ca. SOPC 9.1) which I cannot use the BFM's with (Qsys will produce errors, not the same as yours). The general issue is that my problematic components have incorrect or inconsistent interface parameter settings which work "OK" for synthesis generation, but cause problems for the BFM generation program. 

 

My suggestion is that you review other Qsys messages prior to the error for possible indicators of the problems it might have with your component, or step back and create an empty "foo" component and populate it with your existing component TCL piece by piece until it breaks (or similar debug since you aren't getting a meaningful error message).
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Altera_Forum
Honored Contributor II
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Thanks for the reply Ted. When there's nobody locally that's working on this stuff, it's nice to have someone out there that's willing to take the time to bat ideas back and forth with. 

 

I ended up getting this to work but I'm still not sure what caused it. There wasn't anything in the Qsys messages that seemed to be a problem so I followed your advice and started with a shell of a component with a new tcl file and added the guts of the component. There must have been something broken in the tcl but I didn't whittle it down to a single cause. Hopefully it's clear sailing from here on out :)
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