Can't use 'numeric_std_unsigned' package in Quartus prime lite edition v15.1

Altera_Forum · ‎03-18-2016

I'm using quartus prime lite edition v15.1, trying to write a register file in vhdl. In my code i need to use ' numeric_std_unsigned' package, but an error pops up saying :

--- Quote Start ---

Error (10481): VHDL Use Clause error : design library "IEEE" does not contain primary unit "NUMERIC_STD_unsigned". Verify that the primary unit exists in the library and has been successfully compiled.

--- Quote End ---

I checked VHDL'08 in compiler settings but the error is still there.I think that quartus prime has incomplete support for VHDL'08 and i cann't use some packages

so, it'd be great help if any one can tell me what to do to be able to use 'numeric_std_unsigned' package.

Here's my code:


library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use IEEE.numeric_std_unsigned.all;
 entity regfile is
 port(        clk: in STD_LOGIC;
               regwrite: in STD_LOGIC;  
               rs, rt, rd: in STD_LOGIC_VECTOR(1 downto 0); 
               data_in: in STD_LOGIC_VECTOR(15 downto 0); 
              rd1, rd2: out STD_LOGIC_VECTOR(15 downto 0)); 
 end;
 architecture behave of regfile is type registerFile is
     array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
     signal registers: registerFile;
 begin 
 process(clk) begin
    if rising_edge(clk) then 
       if regwrite='1' then
       registers(to_integer(rd)) <= data_in; 
       end if;
    end if;
 end process;
 
process(all)
 begin
      if (to_integer(rs)=0) 
        then rd1 <= X"0000"; 
          else rd1 <= registers(to_integer(rs)); 
     end if;
   if (to_integer(rt)=0) 
     then rd2 <= X"0000";
     else rd2 <= registers(to_integer(rt));
   end if;
 end process; 
end;

Altera_Forum · ‎03-18-2016

name is "numeric_std" without that extra unsigned

Altera_Forum · ‎03-18-2016

I already tried it. New error occurs related to 'to_integer' it says :

-->can't determine type of object at 'to_integer', found 0 possible types !

Altera_Forum · ‎03-18-2016

try

to_integer(unsigned(x));

Altera_Forum · ‎03-18-2016

thanks it worked, BUT now it's saying : Error (12007): Top-level design entity "Part1" is undefined

( part1 is the name of my project)

Altera_Forum · ‎03-18-2016

Oh i forgot that the name of entity is different from the name of the project, i modified it..Everything is Okay now.

Altera_Forum · ‎03-18-2016

--- Quote Start ---

name is "numeric_std" without that extra unsigned

--- Quote End ---

numeric_std_unsigned is basically the VHDL standard version of the synopsys package std_logic_unsigned. it allows you to treat std_logic_vectors as unsigned values. it was added in VHDL 2008, along with numeric_std_signed.

Quartus does only support minor features of VHDL 2008 - mostly just the easier to use features (like generates and case statement changes). Support for anything useful and major like the new packages has not arrived (and Im guessing unlikely to arrive until some major customers request it).

The (small) list of supported features can be found here: http://quartushelp.altera.com/15.0/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm

Vivado now has better 2008 support (though it's still nowhere near complete).

If you really must have 2008 support - I think synplyfy has it.

Altera_Forum · ‎03-18-2016

Many thanks for the info :D