Can the Cyclone V's FPGA handle a 1 Gigabit long shift register?

[Altera_Forum]

I've been studying Verilog for about a week now moving from c/c++, 

but was wondering if something like this was possible to create a shift register that was 1 Gigabit long?  Double checking before sending it over USB Blaster II for the board's very first project.  I updated an example Intel/Altera had posted for a serial in serial out  with a clock and shift enable. Here is the change I made:  module Gigabit_Shift_Register(clk,   shift,  sr_in,  sr_out,  );    input clk, shift;  input sr_in;  output sr_out;   reg [999999999:0] sr;   always@(posedge clk)  begin  if (shift == 1'b1)  begin  sr[999999999:1] <= sr[999999998:0];  sr[0] <= sr_in;  end  end    assign sr_out = sr[999999999];  endmodule

[Altera_Forum]

And you got this to compile for some Cyclone V device without error? I don't think so. 

 Even the very largest Cyclone V device has only 301K logic elements, a total of 450K registers, which is off by a factor of ~2000 from your 1G register requirement.  You might be able to get a 250K long shift register and still have enough logic resources to do something else. But nowhere near 1G.

[Altera_Forum]

Why would you need such a big shift register? What are you trying to achieve? If you need to buffer that much data it would probably make more sense to deserialize it and write it in an external RAM through a DMA core. It may not be the easiest project to start with HDL design though.