Cannot create an Internal Memory Initialization (.hex) File

[Altera_Forum]

Hello, 

I'm a beginner in Nios II software development. I used the Quartus 13.0, the Qsys and the Nios II EDS for Eclipse to create the count_binary example for the CycloneIII_3c25 Starter Kit. Everything is OK if "Run As -> Nios II Hardware" is used.   But I cannot create an Internal Boot Memory Initialization (.hex) File.   I follow the steps to create memory initialization files in the Nios II Software Developer's Handbook. 1. Right-click the application project. 2. Point to Make targets and click Build to open the Make Targets dialog box. 3. Select mem_init_generate. 4. Click Build. 5. Add the .qip (meminit.qip) file to the Quartus II project.   But I cannot find the .hex files   6. Recompile the Quartus II project. After it I see the warning "Can't find design file <Project name>_mem.hex"   There is another way to create memory initialization file - to use the mem_init.mk But how one can include this file in the application makefile and how a target can be set properly is unknown.   Any idea?   Regards,   tduty

[Altera_Forum]

Hi, 

 I repeated everything more thoroughly. This time the .hex file was created. Then I chose "Assignments->Settings->Files", added meminit.qip to the project, then recompiled it and programmed the Cyclone III using the new .sof   I was ready to see how my application could start from the internal memory. I pressed the CPU_RESET button on my board but nothing changed.  I verified that the reset vector points to 0x0000_8000 i.e. the internal memory beginning (0x0000_8000) So my application loaded as I believe during the FPGA configuring should run.  I examined the board scheme and guessed that the CPU_RESET button did not emulate anything like Power reset.  So I must do it myself somehow  Any idea?  Regards,  tduty

[Altera_Forum]

You shouldn't need to reset, the CPU should start running your application as soon as you configured the FPGA with your new .sof.

[Altera_Forum]

Thank you, Daixiwen! 

 Unfortunately my CPU does not start after configuration. May be the reason is that I use the Altera Nios II Hardware Device Tutorial example for I don't know what tricks the Altera inserts to limit user's possibility in project modifying.  Obviously my new .sof is not able to work. I believe every application section contains in the internal memory. But I don't know how to check it.  To verify everything was done correctly I created this project once more.  The result is the same.  What is wrong?  Regards, tduty

[Altera_Forum]

Does it work when you upload the elf file to the FPGA through the EDS? 

Are you sure your software project uses the bsp corresponding to your hardware project?

[Altera_Forum]

Hello, Daixiwen! 

 Every time I get the .elf file I implement "Run As->Nios II Hardware". The application is loaded into FPGA and runs. Leds flash displaying the working counter, the Nios II - Eclipse CDT Build Console displays the numbers from counter outputs. Then I stop the process and then repeat creating the application (I delete the project and BSP from the software folder) Then I create memory initialization files, add meminit.qip to the hardware project, recompile it and configure the FPGA.  But the application does not work.  The bsp in my software project is created by the Nios II - Eclipse with the application project cimultaneously.  Regards, tduty

[Altera_Forum]

This looks fine. Do you also use an external memory, or do you have only the internal one? If you have several memories, can you check in the bsp settings that at least the application's boot and text sections are in the internal memory? 

If it's still not working, then I suggest to use signaltap on the CPU's instruction and data masters, and use a power up trigger to see what the CPU is doing when the FPGA goes out of configuration.

[Altera_Forum]

Not something silly like trying to use the /f nios without a real license? 

Where it will only work with the jtag debug attached?

[Altera_Forum]

Hello, 

Thank you for your advices.  1. I don’t know where to look for the application boot section but I found others.  From Linker Script tab: Linker Section Name Linker Region Name Memory Device Name .bss onchip_mem onchip_mem .entry reset onchip_mem .exceptions onchip_mem onchip_mem .heap onchip_mem onchip_mem .rodata onchip_mem onchip_mem .rwdata onchip_mem onchip_mem .stack onchip_mem onchip_mem .text onchip_mem onchip_mem  From Linker Memory Regions tab: Linker Region Name Address Range Memory Device Name onchip_mem 0x00008020-0x0000CFFF onchip_mem reset 0x00008000-0x0000801F onchip_mem  I guess the reset vector points to the application boot section or to the crt0.S startup code. So everything must be loaded into the onchip memory.  2. I don’t know how to use signaltap on the CPU's instruction and data masters, and use a power up trigger. So I must study how to do it. Unfortunately too many handbooks cannot be read simultaneously. Where to find the necessary text?  3. I use the Nios II/s.  Indeed my application works when I use “Run As-> Nios II Hardware” only for the time limited. I suppose something from the example settings prevents me to achieve the success if I try to create my .hex file end the new .sof.  Regards. tduty

[Altera_Forum]

Sorry the boot section is .entry. Everything looks fine. 

I think there is a chapter about SignalTap in the Quartus manual. It takes some time to learn to use the tool, but it's not time wasted. It is a very useful and powerfull debugging tool, and you'll need it later. So take the time to learn it! How do you check if your software is running? Could you for example turn a led on or off as the first instruction in main.c, just to check that the software doesn't crash later?

[Altera_Forum]

--- Quote Start ---  Hello, Daixiwen!  Every time I get the .elf file I implement "Run As->Nios II Hardware". The application is loaded into FPGA and runs. Leds flash displaying the working counter, the Nios II - Eclipse CDT Build Console displays the numbers from counter outputs. Then I stop the process and then repeat creating the application (I delete the project and BSP from the software folder) Then I create memory initialization files, add meminit.qip to the hardware project, recompile it and configure the FPGA.  But the application does not work.  The bsp in my software project is created by the Nios II - Eclipse with the application project cimultaneously.  Regards, tduty  --- Quote End ---    I recall that in certain versions of NIOS II Eclipse tools, after you created the memory initialization files, you have to open them in quartus: Upon opening of the file, you would be prompted to enter the word size of the memory file, which defaults to 8 (bits). While Nios processer is 32-bit, you simply change it to 32bits, then save and close the file, recompile the project.  I don't know why it's relevant to change the word size of the init file, but apparently it makes a difference in the results.

[Altera_Forum]

Hello, Daixiwen! 

Thank you for your patience and inspiriting advices. Of course, I will study the SignalTap chapter and try to do you advised. Now how my experiments are fulfilled. I use the Nios II Hardware Device Tutorial Design Example. At first I strictly followed the tutorial - developed the hardware project, the Qsys project and then the Nios II SBT for Eclipse project - count_binary. Then I used <project>(right click)->Run As->Nios II Hardware. As I can guess the compiled and linked application file (.elf) is loaded into the onchip memory and then leds begin to blink and the console window displays numbers from counter.  I modified the projects - inserted the buttons and edge-sensitive interrupts and made a little C-code change - to provide the program exit after the button 2 was pressed.  Everything works fine if "Run As" is used.  My board is tied to my PC by the USB-blaster cable. Sometimes earlier I got messages about time-limited project used and then was to recompile the hardware project.. So I tried to create my own projects similar to the origin ones.  The hardware and Qsys projects were created. But the software project is still not ready because I must learn how the HAL BSP can be created in order not to use the count_binary template.  Everything last created works fine in the "Run As" mode. No messages concerning time limits are sent. Unfortunately any attempt to get the .hex and the new .sof files fails - the new .sof file downloads but all leds begin to shine permanently as if the old .sof was downloaded.  Sorry for the not formatted tables in the last message. In the Quick Reply window the tables were displayed correctly but after posting their data blended.  Regards,  tduty

[Altera_Forum]

Hello, benc! 

 I've done you advised but nothing changed. To be able to save the .hex file after it's opened and the word size is changed to 32 I was to change a symbol in the file and then to restore it. Without it I could not save (unchanged) file.   By the way I noticed the meminit.qip file contains the only string, i.e.  set_global_assignment -name SEARCH_PATH $::quartus(qip_path)  Is it enough for Quartus compiler to find the necessary .hex file?   Regards, tduty

[Altera_Forum]

You should check the settings for the internal memory block in QSys. It's there that you indicate that you want to use a .hex file, and its name. 

IIRC the .hex file needs to be in the project's main folder. Not in QSys' folder, or any place else.

[Altera_Forum]

Hello, Daixiwen! 

I moved the .hex file to the folder where my Quartus hardware project exists. Cimpilation time increased twice.  But the result was the same - nothing worked after congiguration  Ragards

[Altera_Forum]

I will share what I have done in my working project: 

 I am using Quartus II ver12.1 web edition with NIOS II Eclipse 12.1, first, for NIOS II processor system, I have the the setup in Qsys tool as shown in img1.https://www.alteraforum.com/forum/attachment.php?attachmentid=8209   then I build my C source project in NIOS IDE, and created the required memory initialization file for the on-chip memory (connected to both instruction and data master of NIOS processor) in the following default location: C:\altera\cryosystem\software\cryosystem1040\mem_init.hex along with meminit.qip and meminit.spd these files are generated by Eclipse and are not included in Quartus project at this point.  What I do next is go back to Quartus, and open the hex file in quartus, as shown in img2.https://www.alteraforum.com/forum/attachment.php?attachmentid=8206  I change that to 32, then you get correct memory boundaries as shown in img3.https://www.alteraforum.com/forum/attachment.php?attachmentid=8207  Then you can save and replace the original hex file, checked that the saved file is included in the project, as in img3.  Finally when the quartus project is compiled, you can look at the compilation report as shown in img4.https://www.alteraforum.com/forum/attachment.php?attachmentid=8208  My on-chip memory component will be initialized with the hex file when the generated sof is loaded.  I hope this answer some of your questions.

[Altera_Forum]

Hello, benc! 

 I'll try you suggested on Monday and will reply.  Thank you.  Regards,  tduty

[Altera_Forum]

Hello, benc! 

 Thank you for your screen shots. I did everything as you wrote but my application did not work.  I examined the differences in your and my projects and noticed you did not use the jtag uart, but I did.  I don't know why the example author advised to use this component because later nothing was done with it. I deleted it. And after fulfilling all steps I got the working application.  To make sure that the jtag uart prevented from the success I repeated projects creation some times - replacing and deleting this component. Though I've got some experience not every time my results coincided. Very rare the checksum of the .sof file were equal to the previous one. Sometimes after saving the .hex file I did not find it in the file window of the Settings pad and so I was to manually add it. Of course I could do mistakes but I believe the Quartus is capricious.   My finding is - the jtag uart prevented from success.  Thank you for your help in particular for your screen shots.  I would like to thank Daixiwen too - I'll follow his advices.  Too many issues are still unsolved.  Regards,  tduty

[Altera_Forum]

In some driver implementations, the JTAG UART driver hangs the CPU if the nios console isn't connected. This could be what happened here? Do you have any command in your application that writes something to the console? In that case try to switch a LED before any console print, and check if you get at least a change on the LEDs before the CPU hangs.

[Altera_Forum]

Hello, Daixiwen! 

 Right you are. In the example there is some output to the Nios II console and I've forgotten the jtag uart is used to do it. I deleted everything concerning this output from the application. And now inspite of the jtag uart presence my application starts just after FPGA configuration.  But I did not understand your words - "JTAG UART driver hangs the CPU if the Nios console isn't connected." I beleive my Nios console is connected because if I implement "Run As" the data is displayed in the console.  Now I am to create my BSP project. Though I read too many tutorials the Nios II Software Developer's Handbook seems to be written not for beginners - it contains "steps to implement" something but does not describe how to do it.  Some items are discribed in other books (Embedded Design Handbook etc.) So a beginner is in the dark. But it is his issue.  Regards, tduty

[Altera_Forum]

Just one explanation more. 

 Of course I described two various situations - one with jtag uart present but not used in my application and another one when it is used and I fulfill "Run As".  Regards