Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17255 Discussions

Capturing Data

Altera_Forum
Honored Contributor II
‎11-24-2009 09:32 AM
1,078 Views

hi. Timing simulation is done for the sin waveform. The output is only valid when the signal out_valid is high. So, can i just capturing the valid output signal and save it using Quartus II? 

 

Or i have to manually write a program to filter out unwanted output? 

 

Thanks
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Altera_Forum
Honored Contributor II
‎12-30-2009 01:48 AM
446 Views

Could you post your code?

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Altera_Forum
Honored Contributor II
‎01-17-2010 03:03 AM
446 Views

Do you mean the verilog code? Is it related to it?

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Altera_Forum
Honored Contributor II
‎01-17-2010 03:25 PM
446 Views

Thanks to all

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