tried to create Carry Look-Ahead Adder by gate level style in verilog.
it works, but exactly as a simple ripple adder would work. maybe after tickling with synthesis options it's performance increase is negligible.looks like synthesis synthesizes all of this excessive "Look-Ahead" circuit because it finds that boolean result would be same as with ripple adders.
i have read here and there that making carry look aheads has no effect because of the FPGA architecture itself. and that simple "+" opertion already tries to drive carry in an efficient way.
An old document at
altera.com describes that in MAXII+PLUS there was a "General Synthesis Options" -> "Default Synthesis Style" option and if you would change i'ts content carry look aheads did synthesized correctly but in Quartus 13.1 there is no such logic option. so.. is there a way to implement a Parallel Carry Look Ahead Adder by Logic Cells? i mean by LUT s, when you do not have any built in fast adder hardware in your FPGA.
