Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17256 Discussions

Checksum variance of compiled pof/sof images from one version of Quartus to another.

Altera_Forum
Honored Contributor II
1,977 Views

Hi Folks: 

 

I'm trying to recover command of an old project from 2003. It's running on a Flex10K40RC208 with the .pof being stored on a EPC2. The orig .pof was complied  

under Quartus 2.3. The source code is in .gdf (schematic) format. It's not written in AHDL, VHDL, or Verilog. I don't have a working copy of Quartus 2.3 anymore. The earliest web version I have is Quartus 3.0. When I compile the the source code in Quartus 3.0, the checksum I get for the resultant .pof file is the same only for the first 3 or 4 most sig hex digits. Worse yet, when I program that .pof the functionality of the FPGA is nil. Now, I can reprogram the orig archived .pof, and I can also reprogram the .pof I read off the epc2, and I regain my functionality.  

 

I'm sure the source file I'm working from is the orig source code for the original .pof. It seems that different versions of Quartus are compiling the .gdf (schematic) file different from one version to another.  

 

Questions. 

 

1) How could I obtain a version of Quartus that's the same version the project was orig compiled in? 

Again; the earliest version off the web I could find was Quartus 3.0.  

2) Is there a way to set the compile flags to set the compiler to act like a previous version? 

3) What could cause such a radical deviation in the quality of functionality. From an image that has worked non stop for 12 years + to one that does not work at all? 

 

Thanks for Considering This. 

Andrew
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
1,179 Views

1. You'll probably need to contact altera (directly or via your FAE). Have you raised a ticket via mysupport? 

2. No 

3. If the design contains asynchronous elements, LCELLS to manually delay signals and other poor design practice (like no timing specs) it can quite easily cause differences from one compile to another, simply by a different placement. I have seen designs fail and pass based on changes like this (and even seen people ship designs with signal tap left in simply because it worked!).  

 

make sure you get exactly the same version, as different services packs and windows/linux versions will produce different results.
0 Kudos
Reply