Clock Constraints for a Clock signal created with a Nios software-driven Output Port

[Altera_Forum]

I have a test bed for my DSP logic design in a Cyclone III, and in this I use the Nios2 processor to control the test process (it is easier for me to test it using the NIOS2 debugger) 

 The DSP module I am currently testing has 1 main clock (PPL_CLK). In the test bed these clocks are driven by output ports of the Nios2 processor, which in turn has a 50MHz oscillator (OSC_CLK) as its main clock.   In my test code I toggle the port signals to simulate the clock. I can control the ON part of each pulse, which is about 1us, the OFF part is of about 100 us (since the software has to do some other stuff during that time)   I am having a hardtime figuring how to define the clock constraints for the DSP module: How should I relate my PPL_CLK to the OSC_CLK? Can I treat both of them as independent clocks? (i.e. declare them using create_clock) or should I derive PPL_CLK from OSC_CLK using create_generated_clock?   Although we could trace PPL_CLK to OSC_CLK, their phase and frequency relationship is foggy, since there is software involved.   Please see the attached block diagram... Thanks

[Altera_Forum]

Generating a clock from FPGA logic is a bad idea, because the glitches caused by the LUT can be seen as extra clock edges by some cells and would make your logic crash or behave strangely. If possible, it is far better to use the main clock and only control a clock enable signal from the CPU.

[Altera_Forum]

I think you can make the DSP block as a Custom component which acts as an avalon slave to Nios II processor rather than driving a clock from Nios II to DSP Module 

 Regards M Kalyansrinivas