Hi all
In my design I am using the megacore function "DDR2 SDRAM Controller with UniPHY". This module produces a clock called "DDR_CNT|pp_ddr2_inst|pp_ddr2_p0_pll_afi_clk".
I am trying to remove paths in my design that fail timing requirements, using the TimeQuest Timing Analyser. On all paths that have a source register clocked by the afi_clk, that have the destination register clocked by some other clock, the path fails timing. The cause seems to be that the clock routing delay is not compensated (the DDR2 PLL is in non-compensating mode) and the clock path has a delay of about 5.6 ns. The destination registers are typically clocked at 160MHz (6.25ns period) which means the data path only has about 0.65ns to actually "do stuff".
1. Is this an issue with the way TimeQuest reports the path, which crosses between the two clock domains, or a genuine issue for the design? I assume the latter!
2. Whats the best way to solve the issue!
Thanks very much in advance
Chris Parkinson
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I am using Quartus II 32-bit version 13.1.0 Build 162
The device is a Stratix III EP3SL200F1152C4
